forked from PAWPAW-Mirror/lib_xua
Moved AN00246 from xCORE-200 to xCORE.ai MC Audio Board
This commit is contained in:
xross
@@ -1,146 +1,56 @@
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// Copyright 2016-2022 XMOS LIMITED.
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// Copyright 2017-2022 XMOS LIMITED.
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// This Software is subject to the terms of the XMOS Public Licence: Version 1.
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#include <xs1.h>
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#include <platform.h>
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#include <timer.h>
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#include <stdint.h>
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#include "xua.h"
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#include "i2c.h" /* From lib_i2c */
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#include "../../shared/apppll.h"
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#include "cs5368.h"
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#include "cs4384.h"
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on tile[0]: out port p_ctrl = XS1_PORT_8D;
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port p_i2c = on tile[0]:XS1_PORT_4A;
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/* p_ctrl:
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* [0:3] - Unused
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* [4] - EN_3v3_N
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* [5] - EN_3v3A
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* [6] - EXT_PLL_SEL (CS2100:0, SI: 1)
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* [7] - MCLK_DIR (Out:0, In: 1)
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*/
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#define EXT_PLL_SEL__MCLK_DIR (0x80)
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/* General output port bit definitions */
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#define P_GPIO_DSD_MODE (1 << 0) /* DSD mode select 0 = 8i/8o I2S, 1 = 8o DSD*/
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#define P_GPIO_DAC_RST_N (1 << 1)
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#define P_GPIO_USB_SEL0 (1 << 2)
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#define P_GPIO_USB_SEL1 (1 << 3)
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#define P_GPIO_VBUS_EN (1 << 4)
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#define P_GPIO_PLL_SEL (1 << 5) /* 1 = CS2100, 0 = Phaselink clock source */
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#define P_GPIO_ADC_RST_N (1 << 6)
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#define P_GPIO_MCLK_FSEL (1 << 7) /* Select frequency on Phaselink clock. 0 = 24.576MHz for 48k, 1 = 22.5792MHz for 44.1k.*/
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#define DAC_REGWRITE(reg, val) result = i2c.write_reg(CS4384_I2C_ADDR, reg, val);
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#define DAC_REGREAD(reg) data = i2c.read_reg(CS4384_I2C_ADDR, reg, result);
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#define ADC_REGWRITE(reg, val) result = i2c.write_reg(CS5368_I2C_ADDR, reg, val);
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out port p_gpio = on tile[0]:XS1_PORT_8C;
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void AudioHwConfig2(unsigned samFreq, unsigned mClk, unsigned dsdMode, unsigned sampRes_DAC, unsigned sampRes_ADC, client interface i2c_master_if i2c)
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/* Note, this runs on Tile[0] */
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void ctrlPort()
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{
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unsigned char gpioVal = 0;
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i2c_regop_res_t result;
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/* Set master clock select appropriately and put ADC and DAC into reset */
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if (mClk == MCLK_441)
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// Drive control port to turn on 3V3 and set MCLK_DIR
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// Note, "soft-start" to reduce current spike
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// Note, 3v3_EN is inverted
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for (int i = 0; i < 30; i++)
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{
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gpioVal = P_GPIO_USB_SEL0 | P_GPIO_USB_SEL1;
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p_ctrl <: EXT_PLL_SEL__MCLK_DIR | 0x30; /* 3v3: off, 3v3A: on */
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delay_microseconds(5);
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p_ctrl <: EXT_PLL_SEL__MCLK_DIR | 0x20; /* 3v3: on, 3v3A: on */
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delay_microseconds(5);
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}
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else
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{
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gpioVal = P_GPIO_USB_SEL0 | P_GPIO_USB_SEL1 | P_GPIO_MCLK_FSEL;
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}
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p_gpio <: gpioVal;
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/* Allow MCLK to settle */
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delay_microseconds(20000);
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/* Take ADC out of reset */
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gpioVal |= P_GPIO_ADC_RST_N;
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p_gpio <: gpioVal;
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/* Configure ADC for I2S slave mode via I2C */
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unsigned dif = 0, mode = 0;
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dif = 0x01; /* I2S */
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mode = 0x03; /* Slave mode all speeds */
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/* Reg 0x01: (GCTL) Global Mode Control Register
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* Bit[7]: CP-EN: Manages control-port mode
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* Bit[6]: CLKMODE: Setting puts part in 384x mode
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* Bit[5:4]: MDIV[1:0]: Set to 01 for /2
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* Bit[3:2]: DIF[1:0]: Data Format: 0x01 for I2S, 0x02 for TDM
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* Bit[1:0]: MODE[1:0]: Mode: 0x11 for slave mode
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*/
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ADC_REGWRITE(CS5368_GCTL_MDE, 0b10010000 | (dif << 2) | mode);
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/* Reg 0x06: (PDN) Power Down Register */
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/* Bit[7:6]: Reserved
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* Bit[5]: PDN-BG: When set, this bit powers-own the bandgap reference
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* Bit[4]: PDM-OSC: Controls power to internal oscillator core
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* Bit[3:0]: PDN: When any bit is set all clocks going to that channel pair are turned off
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*/
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ADC_REGWRITE(CS5368_PWR_DN, 0b00000000);
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/* Configure DAC with PCM values. Note 2 writes to mode control to enable/disable freeze/power down */
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/* Take DAC out of reset */
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gpioVal |= P_GPIO_DAC_RST_N;
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p_gpio <: gpioVal;
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delay_microseconds(500);
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/* Mode Control 1 (Address: 0x02) */
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/* bit[7] : Control Port Enable (CPEN) : Set to 1 for enable
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* bit[6] : Freeze controls (FREEZE) : Set to 1 for freeze
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* bit[5] : PCM/DSD Selection (DSD/PCM) : Set to 0 for PCM
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* bit[4:1] : DAC Pair Disable (DACx_DIS) : All Dac Pairs enabled
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* bit[0] : Power Down (PDN) : Powered down
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*/
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DAC_REGWRITE(CS4384_MODE_CTRL, 0b11000001);
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/* PCM Control (Address: 0x03) */
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/* bit[7:4] : Digital Interface Format (DIF) : 0b0001 for I2S up to 24bit
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* bit[3:2] : Reserved
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* bit[1:0] : Functional Mode (FM) : 0x00 - single-speed mode (4-50kHz)
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* : 0x01 - double-speed mode (50-100kHz)
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* : 0x10 - quad-speed mode (100-200kHz)
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* : 0x11 - auto-speed detect (32 to 200kHz)
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* (note, some Mclk/SR ratios not supported in auto)
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*
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*/
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unsigned char regVal = 0;
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if(samFreq < 50000)
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regVal = 0b00010100;
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else if(samFreq < 100000)
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regVal = 0b00010101;
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else //if(samFreq < 200000)
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regVal = 0b00010110;
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DAC_REGWRITE(CS4384_PCM_CTRL, regVal);
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/* Mode Control 1 (Address: 0x02) */
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/* bit[7] : Control Port Enable (CPEN) : Set to 1 for enable
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* bit[6] : Freeze controls (FREEZE) : Set to 0 for freeze
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* bit[5] : PCM/DSD Selection (DSD/PCM) : Set to 0 for PCM
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* bit[4:1] : DAC Pair Disable (DACx_DIS) : All Dac Pairs enabled
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* bit[0] : Power Down (PDN) : Not powered down
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*/
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DAC_REGWRITE(CS4384_MODE_CTRL, 0b10000000);
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/* Kill the i2c task */
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i2c.shutdown();
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return;
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}
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/* Configures the external audio hardware at startup. Note this runs on Tile[1] */
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void AudioHwInit()
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{
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/* Set USB Mux to micro-b */
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/* ADC and DAC in reset */
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p_gpio <: P_GPIO_USB_SEL0 | P_GPIO_USB_SEL1;
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/* Wait for power supply to come up */
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delay_milliseconds(100);
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/* Use xCORE Secondary PLL to generate *fixed* master clock */
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AppPllEnable_SampleRate(DEFAULT_FREQ);
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delay_milliseconds(100);
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/* DAC setup: For basic I2S input we don't need any register setup. DACs will clock auto detect etc.
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* It holds DAC in reset until it gets clocks anyway.
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* Note, this example doesn't use the ADC's
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*/
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}
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void AudioHwConfig(unsigned samFreq, unsigned mClk, unsigned dsdMode,
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unsigned sampRes_DAC, unsigned sampRes_ADC)
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/* Configures the external audio hardware for the required sample frequency */
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void AudioHwConfig(unsigned samFreq, unsigned mClk, unsigned dsdMode, unsigned sampRes_DAC, unsigned sampRes_ADC)
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{
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i2c_master_if i2c[1];
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par
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{
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i2c_master_single_port(i2c, 1, p_i2c, 10, 0, 1, 0);
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AudioHwConfig2(samFreq, mClk, dsdMode, sampRes_DAC, sampRes_ADC, i2c[0]);
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}
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AppPllEnable_SampleRate(samFreq);
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}
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