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Initial addition of xCORE-200 hardware bit-clock divide (currently not enabled)

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This commit is contained in:
Ross Owen
2015-11-17 11:39:44 +00:00
parent f995c15020
commit f947005eb1
2 changed files with 14 additions and 2 deletions
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3
module_usb_audio/audio.xc
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@@ -109,6 +109,8 @@ extern void device_reboot(void);
#ifndef CODEC_MASTER #ifndef CODEC_MASTER
static inline void doI2SClocks(unsigned divide) static inline void doI2SClocks(unsigned divide)
{ {
//#ifndef __XS2A__
#if 1
switch (divide) switch (divide)
{ {
#if (MAX_DIVIDE > 16) #if (MAX_DIVIDE > 16)
@@ -166,6 +168,7 @@ static inline void doI2SClocks(unsigned divide)
break; break;
#endif #endif
} }
#endif
} }
#endif #endif

13
module_usb_audio/ports/audioports.xc
View File

@@ -20,7 +20,7 @@ void ConfigAudioPorts(
#endif #endif
#if (I2S_CHANS_DAC != 0) || (I2S_CHANS_ADC != 0) #if (I2S_CHANS_DAC != 0) || (I2S_CHANS_ADC != 0)
#ifndef CODEC_MASTER #if !defined(CODEC_MASTER)
buffered out port:32 ?p_lrclk, buffered out port:32 ?p_lrclk,
buffered out port:32 p_bclk, buffered out port:32 p_bclk,
#else #else
@@ -31,7 +31,8 @@ void ConfigAudioPorts(
unsigned int divide) unsigned int divide)
{ {
#ifndef CODEC_MASTER printintln(divide);
#if !defined(CODEC_MASTER)
/* Note this call to stop_clock() will pause forever if the port clocking the clock-block is not low. /* Note this call to stop_clock() will pause forever if the port clocking the clock-block is not low.
* deliver() should return with this being the case */ * deliver() should return with this being the case */
stop_clock(clk_audio_bclk); stop_clock(clk_audio_bclk);
@@ -70,11 +71,19 @@ unsigned int divide)
} }
else else
{ {
//#if defined(__XS2A__)
#if 0
/* Clock bitclock clock block from master clock pin (divided) */
configure_clock_src_divide(clk_audio_bclk, p_mclk_in, divide / 2);
configure_port_clock_output(p_bclk, clk_audio_bclk);
#else
/* bit clock port from master clock clock-clock block */ /* bit clock port from master clock clock-clock block */
configure_out_port_no_ready(p_bclk, clk_audio_mclk, 0); configure_out_port_no_ready(p_bclk, clk_audio_mclk, 0);
/* Generate bit clock block from pin */ /* Generate bit clock block from pin */
configure_clock_src(clk_audio_bclk, p_bclk); configure_clock_src(clk_audio_bclk, p_bclk);
#endif
} }
if(!isnull(p_lrclk)) if(!isnull(p_lrclk))