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- Set I2S clocks to 8mA drive on XS3

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- Set sample-delay on ADC data lines in TDM mode
- Stare some port config code between I2S slave and master modes
This commit is contained in:
xross
2022-09-27 18:02:37 +01:00
parent 6beb1f34ae
commit fe39cd7c11
2 changed files with 20 additions and 26 deletions
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1
lib_xua/src/core/audiohub/xua_audiohub.xc
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@@ -122,7 +122,6 @@ static inline unsigned DoSampleTransfer(chanend ?c_out, const int readBuffNo, co
if(dsdMode == DSD_MODE_DOP) if(dsdMode == DSD_MODE_DOP)
dsdMode = DSD_MODE_OFF; dsdMode = DSD_MODE_OFF;
#endif #endif
#pragma xta endpoint "received_command"
return command; return command;
} }
else else

45
lib_xua/src/core/ports/audioports.xc
View File

@@ -35,11 +35,16 @@ void ConfigAudioPorts(
#if (I2S_CHANS_DAC != 0) || (I2S_CHANS_ADC != 0) #if (I2S_CHANS_DAC != 0) || (I2S_CHANS_ADC != 0)
#if (CODEC_MASTER == 0) #if (CODEC_MASTER == 0)
#ifdef __XS3A__
/* Increase drive strength of clock ports to 8mA */
asm volatile ("setc res[%0], %1" :: "r" (p_bclk), "r" (0x200006));
asm volatile ("setc res[%0], %1" :: "r" (p_lrclk), "r" (0x200006));
#endif
/* Note this call to stop_clock() will pause forever if the port clocking the clock-block is not low. /* Note this call to stop_clock() will pause forever if the port clocking the clock-block is not low.
* deliver() should return with this being the case */ * deliver() should return with this being the case */
stop_clock(clk_audio_bclk); stop_clock(clk_audio_bclk);
if(!isnull(p_lrclk)) if(!isnull(p_lrclk))
{ {
clearbuf(p_lrclk); clearbuf(p_lrclk);
@@ -73,26 +78,13 @@ void ConfigAudioPorts(
configure_out_port_no_ready(p_lrclk, clk_audio_bclk, 0); configure_out_port_no_ready(p_lrclk, clk_audio_bclk, 0);
} }
#if (I2S_CHANS_DAC != 0) if(XUA_PCM_FORMAT == XUA_PCM_FORMAT_TDM)
/* Clock I2S output data ports from clock block */ {
for(int i = 0; i < numPortsDac; i++) for(int i = 0; i < I2S_WIRES_ADC; i++)
{ set_port_sample_delay(p_i2s_adc[i]);
configure_out_port_no_ready(p_i2s_dac[i], clk_audio_bclk, 0); }
}
#endif
#if (I2S_CHANS_ADC != 0) #elif (CODEC_MASTER)
/* Clock I2S input data ports from clock block */
for(int i = 0; i < numPortsAdc; i++)
{
configure_in_port_no_ready(p_i2s_adc[i], clk_audio_bclk);
}
#endif
/* Start clock blocks ticking */
start_clock(clk_audio_bclk);
#else /* CODEC_MASTER */
/* Stop bit and master clock blocks */ /* Stop bit and master clock blocks */
stop_clock(clk_audio_bclk); stop_clock(clk_audio_bclk);
@@ -100,8 +92,9 @@ void ConfigAudioPorts(
/* Clock bclk clock-block from bclk pin */ /* Clock bclk clock-block from bclk pin */
configure_clock_src(clk_audio_bclk, p_bclk); configure_clock_src(clk_audio_bclk, p_bclk);
configure_in_port_no_ready(p_lrclk, clk_audio_bclk);
/* Do some clocking shifting to get data in the valid window */ /* Do some clocking shifting to get data in the valid window */
/* E.g. Only shift when running at 88.2+ kHz TDM slave */ /* E.g. Only shift when running at 88.2+ kHz TDM slave */
int bClkDelay_fall = 0; int bClkDelay_fall = 0;
if(curSamFreq * I2S_CHANS_PER_FRAME * 32 >= 20000000) if(curSamFreq * I2S_CHANS_PER_FRAME * 32 >= 20000000)
@@ -112,6 +105,9 @@ void ConfigAudioPorts(
set_clock_fall_delay(clk_audio_bclk, bClkDelay_fall); set_clock_fall_delay(clk_audio_bclk, bClkDelay_fall);
#endif
#if (I2S_CHANS_DAC != 0) #if (I2S_CHANS_DAC != 0)
/* Clock I2S output data ports from b-clock clock block */ /* Clock I2S output data ports from b-clock clock block */
for(int i = 0; i < I2S_WIRES_DAC; i++) for(int i = 0; i < I2S_WIRES_DAC; i++)
@@ -128,10 +124,9 @@ void ConfigAudioPorts(
} }
#endif #endif
configure_in_port_no_ready(p_lrclk, clk_audio_bclk); /* Start clock blocks ticking */
start_clock(clk_audio_bclk); start_clock(clk_audio_bclk);
#endif
#endif #endif //#if (I2S_CHANS_DAC != 0) || (I2S_CHANS_ADC != 0)
} }