forked from PAWPAW-Mirror/lib_xua
177 lines
6.9 KiB
ReStructuredText
Executable File
177 lines
6.9 KiB
ReStructuredText
Executable File
.. _usb_audio_sec_audio:
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AudioHub/I2S
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............
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The AudioHub task performs many functions. It receives and transmits samples from/to the decoupler or mixer core over an XC channel.
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It also drives several in and out I2S/TDM channels to/from a CODEC, DAC, ADC etc - from now on termed "audio hardware".
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If the firmware is configured with the xCORE as I2S master the requred clock lines will also be driven out from this task also.
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It also has the task of formwarding on and reciving samples to/from other audio related tasks such as S/PDIF tasks, ADAT tasks etc.
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The AudioHub task must be connected to external audio hardware that supports I2S (other modes such as "left justified" can be supported with firmware changes).
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In master mode, the XMOS device acts as the master generating the I2S "Continous Serial Clock (SCK)" typically called the Bit-Clock (BCLK) and the "Word Select (WS)" line typically called left-right clock (LRCLK) signals. Any CODEC or DAC/ADC combination that supports I2S and can be used.
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The LR-clock, bit-clock and data are all derived from the incoming master clock (typically the output of the external oscillator or PLL)
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- This is not part of the I2S standard but is commonly included for synchronizing the internal operation of the analog/digital converters.
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The AudioHub task is implemented in the file ``xua_audiohub.xc``.
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:ref:`usb_audio_codec_signals` shows the signals used to communicate audio between the XMOS device and the external audio hardware.
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.. _usb_audio_codec_signals:
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.. list-table:: I2S Signals
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:header-rows: 1
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:widths: 20 80
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* - Signal
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- Description
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* - LRCLK
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- The word clock, transition at the start of a sample
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* - BCLK
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- The bit clock, clocks data in and out
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* - SDIN
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- Sample data in (from CODEC/ADC to the XMOS device)
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* - SDOUT
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- Sample data out (from the XMOS device to CODEC/DAC)
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* - MCLK
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- The master clock running the CODEC/DAC/ADC
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The bit clock controls the rate at which data is transmitted to and from the external audio hardware.
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In the case where the XMOS device is the master, it divides the MCLK to generate the required signals for both BCLK and LRCLK,
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with BCLK then being used to clock data in (SDIN) and data out (SDOUT) of the external audio hardware.
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:ref:`usb_audio_example_clock_divides` shows some example clock frequencies and divides for different sample rates:
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.. _usb_audio_example_clock_divides:
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.. list-table:: Clock Divide examples
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:header-rows: 1
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:widths: 30 25 25 20
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* - Sample Rate (kHz)
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- MCLK (MHz)
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- BCLK (MHz)
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- Divide
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* - 44.1
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- 11.2896
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- 2.819
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- 4
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* - 88.2
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- 11.2896
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- 5.638
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- 2
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* - 176.4
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- 11.2896
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- 11.2896
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- 1
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* - 48
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- 24.576
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- 3.072
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- 8
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* - 96
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- 24.576
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- 6.144
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- 4
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* - 192
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- 24.576
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- 12.288
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- 2
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The master clock must be supplied by an external source e.g. clock generator, fixed oscillators, PLL etc to generate the two frequencies to support
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44.1kHz and 48kHz audio frequencies (e.g. 11.2896/22.5792MHz and 12.288/24.576MHzrespectively). This master clock input is then provided to the
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external audio hardware and the xCORE device.
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Port Configuration (xCORE Master)
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+++++++++++++++++++++++++++++++++
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The default software configuration is xCORE is I2S master. That is, the XMOS device provides the BCLK and LRCLK signals to the external audio hardware
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xCORE ports and XMOS clocks provide many valuable features for implementing I2S. This section describes how these are configured
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and used to drive the I2S interface.
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.. only:: latex
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.. figure:: images/port_config.pdf
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Ports and Clocks (xCORE master)
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.. only:: html
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.. figure:: images/port_config.png
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Ports and Clocks (xCORE master)
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The code to configure the ports and clocks is in the ``ConfigAudioPorts()`` function. Developers should not need to modify this.
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The xCORE inputs MCLK and divides it down to generate BCLK and LRCLK.
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To achieve this MCLK is input into the device using the 1-bit port ``p_mclk``. This is attached to the clock block ``clk_audio_mclk``, which is in
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turn used to clock the BCLK port, ``p_bclk``. BCLK is used to clock the LRCLK (``p_lrclk``) and data signals SDIN (``p_sdin``) and SDOUT (``p_sdout``).
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Again, a clock block is used (``clk_audio_bclk``) which has ``p_bclk`` as its input and is used to clock the ports ``p_lrclk``, ``p_sdin`` and ``p_sdout``.
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The preceding diagram shows the connectivity of ports and clock blocks.
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``p_sdin`` and ``p_sdout`` are configured as buffered ports with a transfer width of 32, so all 32 bits are
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input in one input statement. This allows the software to input, process and output 32-bit words, whilst the ports serialize and
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deserialize to the single I/O pin connected to each port.
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xCORE-200 series devices have the ability to divide an extenal clock in a clock-block.
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However, XS1 based devices do not have this functionality. In order achieve the reqired master-clock
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to bit-clock/LR-clock divicd on XS1 devices, buffered ports with a transfer width of 32 are also
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used for ``p_bclk`` and ``p_lrclk``. The bit clock is generated by performing outputs of a particular pattern to ``p_bclk`` to toggle
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the output at the desired rate. The pattern depends on the divide between the master-clock and bit-clock.
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The following table shows the required pattern for different values of this divide:
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.. list-table:: Output patterns
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:header-rows: 1
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* - Divide
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- Output pattern
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- Outputs per sample
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* - 2
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- ``0xAAAAAAAA``
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- 2
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* - 4
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- ``0xCCCCCCCC``
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- 4
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* - 8
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- ``0xF0F0F0F0``
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- 8
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In any case, the bit clock outputs 32 clock cycles per sample. In the special case where the divide is 1 (i.e. the bit clock frequency equals
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the master clock frequency), the ``p_bclk`` port is set to a special mode where it simply outputs its clock input (i.e. ``p_mclk``).
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See ``configure_port_clock_output()`` in ``xs1.h`` for details.
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``p_lrclk`` is clocked by ``p_bclk``. In I2S mode the port outputs the pattern ``0x7fffffff``
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followed by ``0x80000000`` repeatedly. This gives a signal that has a transition one bit-clock
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before the data (as required by the I2S standard) and alternates between high and low for the
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left and right channels of audio.
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Changing Audio Sample Frequency
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+++++++++++++++++++++++++++++++
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.. _usb_audio_sec_chang-audio-sample:
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When the host changes sample frequency, a new frequency is sent to
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the audio driver core by Endpoint 0 (via the buffering cores and mixer).
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First, a change of sample frequency is reported by sending the new frequency over an XC channel. The audio core
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detects this by checking for the presence of a control token on the channel channel
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Upon receiving the change of sample frequency request, the audio
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core stops the I2S/TDM interface and calls the CODEC/port configuration
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functions.
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Once this is complete, the I2S/TDM interface (i.e. the main look in AudioHub) is restarted at the new frequency.
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