forked from PAWPAW-Mirror/lib_xua
153 lines
4.0 KiB
Plaintext
153 lines
4.0 KiB
Plaintext
#include <xs1.h>
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#include <platform.h>
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#include <print.h>
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#include "devicedefines.h"
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#include "audioports.h"
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extern port p_mclk_in;
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extern clock clk_audio_mclk;
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extern clock clk_audio_bclk;
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void ConfigAudioPorts(
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#if (I2S_CHANS_DAC != 0) || (DSD_CHANS_DAC != 0)
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buffered out port:32 p_i2s_dac[],
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int numPortsDac,
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#endif
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#if (I2S_CHANS_ADC != 0)
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buffered in port:32 p_i2s_adc[],
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int numPortsAdc,
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#endif
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#if (I2S_CHANS_DAC != 0) || (I2S_CHANS_ADC != 0)
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#if !defined(CODEC_MASTER)
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buffered out port:32 ?p_lrclk,
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buffered out port:32 p_bclk,
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#else
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in port ?p_lrclk,
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in port p_bclk,
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#endif
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#endif
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unsigned int divide, unsigned curSamFreq)
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{
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#if !defined(CODEC_MASTER)
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/* Note this call to stop_clock() will pause forever if the port clocking the clock-block is not low.
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* deliver() should return with this being the case */
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stop_clock(clk_audio_bclk);
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if(!isnull(p_lrclk))
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{
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clearbuf(p_lrclk);
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}
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clearbuf(p_bclk);
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#if (I2S_CHANS_ADC != 0)
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for(int i = 0; i < numPortsAdc; i++)
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{
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clearbuf(p_i2s_adc[i]);
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}
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#endif
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#if (I2S_CHANS_DAC != 0)
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for(int i = 0; i < numPortsDac; i++)
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{
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clearbuf(p_i2s_dac[i]);
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}
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#endif
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#if defined(__XS2A__)
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/* Clock bitclock clock block from master clock pin (divided) */
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configure_clock_src_divide(clk_audio_bclk, p_mclk_in, (divide/2));
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configure_port_clock_output(p_bclk, clk_audio_bclk);
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#else
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/* For a divide of one (i.e. bitclock == master-clock) BClk is set to clock_output mode.
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* In this mode it outputs an edge clock on every tick of itsassociated clock_block.
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*
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* For all other divides, BClk is clocked by the master clock and data
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* will be output to p_bclk to generate the bit clock.
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*/
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if (divide == 1) /* e.g. 176.4KHz from 11.2896 */
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{
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configure_port_clock_output(p_bclk, clk_audio_mclk);
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/* Generate bit clock block straight from mclk */
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configure_clock_src(clk_audio_bclk, p_mclk_in);
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}
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else
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{
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/* bit clock port from master clock clock-clock block */
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configure_out_port_no_ready(p_bclk, clk_audio_mclk, 0);
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/* Generate bit clock block from pin */
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configure_clock_src(clk_audio_bclk, p_bclk);
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}
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#endif
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if(!isnull(p_lrclk))
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{
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/* Clock LR clock from bit clock-block */
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configure_out_port_no_ready(p_lrclk, clk_audio_bclk, 0);
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}
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#if (I2S_CHANS_DAC != 0)
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/* Clock I2S output data ports from clock block */
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for(int i = 0; i < numPortsDac; i++)
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{
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configure_out_port_no_ready(p_i2s_dac[i], clk_audio_bclk, 0);
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}
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#endif
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#if (I2S_CHANS_ADC != 0)
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/* Clock I2S input data ports from clock block */
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for(int i = 0; i < numPortsAdc; i++)
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{
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configure_in_port_no_ready(p_i2s_adc[i], clk_audio_bclk);
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}
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#endif
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/* Start clock blocks ticking */
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start_clock(clk_audio_bclk);
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#else /* CODEC_MASTER */
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/* Stop bit and master clock blocks */
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stop_clock(clk_audio_bclk);
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/* Clock bclk clock-block from bclk pin */
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configure_clock_src(clk_audio_bclk, p_bclk);
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/* Do some clocking shifting to get data in the valid window */
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/* E.g. Only shift when running at 88.2+ kHz TDM slave */
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int bClkDelay_fall = 0;
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if(curSamFreq * I2S_CHANS_PER_FRAME * 32 >= 20000000)
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{
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/* 18 * 2ns = 36ns. This results in a -4ns (36 - 40) shift at 96KHz and -8ns (36 - 44) at 88.4KHz */
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bClkDelay_fall = 18;
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}
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set_clock_fall_delay(clk_audio_bclk, bClkDelay_fall);
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#if (I2S_CHANS_DAC != 0)
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/* Clock I2S output data ports from b-clock clock block */
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for(int i = 0; i < I2S_WIRES_DAC; i++)
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{
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configure_out_port_no_ready(p_i2s_dac[i], clk_audio_bclk, 0);
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}
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#endif
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#if (I2S_CHANS_ADC != 0)
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/* Clock I2S input data ports from clock block */
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for(int i = 0; i < I2S_WIRES_ADC; i++)
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{
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configure_in_port_no_ready(p_i2s_adc[i], clk_audio_bclk);
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}
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#endif
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configure_in_port_no_ready(p_lrclk, clk_audio_bclk);
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start_clock(clk_audio_bclk);
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#endif
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}
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