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WIP + get DAC config running

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This commit is contained in:
Ed Clarke
2018-10-26 11:25:39 +01:00
parent 770c11b3f0
commit 161b934b8f
8 changed files with 198 additions and 165 deletions
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1
.gitignore vendored
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@@ -26,3 +26,4 @@ _build*
build/
.build*
*.pyc
xscope.xmt

4
examples/xua_lite_example/Makefile
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@@ -4,7 +4,9 @@ TARGET = RPI_HAT_60QFN.xn
# The flags passed to xcc when building the application
XCC_FLAGS = -fcomment-asm -Xmapper --map -Xmapper MAPFILE -O3 -report \
-g -Wno-unused-function -Wno-timing -DXUD_SERIES_SUPPORT=XUD_X200_SERIES -DUSB_TILE=tile[0]
-g -Wno-unused-function -Wno-timing -DXUD_SERIES_SUPPORT=XUD_X200_SERIES -DUSB_TILE=tile[0] \
-D XUA_LITE=1
#-DSDA_HIGH=2 -DSCL_HIGH=1 -fxscope

3
examples/xua_lite_example/config.xscope Normal file
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@@ -0,0 +1,3 @@
<xSCOPEconfig ioMode="basic" enabled="true">
<Probe name="Value" type="CONTINUOUS" datatype="INT" units="Value" enabled="true"/>
</xSCOPEconfig>

295
examples/xua_lite_example/src/AudioConfig.xc
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@@ -3,6 +3,7 @@
#include <platform.h>
#include <print.h>
#include <stdio.h>
#include "i2c.h"
@@ -51,168 +52,156 @@
// TLV320DAC3101 easy register access defines
//#define DAC3101_REGWRITE(reg, val) {data[0] = val; i2c_master_write_reg(DAC3101_I2C_DEVICE_ADDR, reg, data, 1, i2c);}
#define DAC3101_REGWRITE(reg, val)
#define DAC3101_REGWRITE(reg, val) {i_i2c.write_reg(DAC3101_I2C_DEVICE_ADDR, reg, val);}
void AudioHwConfigure(unsigned samFreq)
void AudioHwConfigure(unsigned samFreq, client i2c_master_if i_i2c)
{
// Take DAC out of reset.
//p_gpio <: 1;
par
// Wait for 1ms
delay_milliseconds(1);
// Set register page to 0
DAC3101_REGWRITE(DAC3101_PAGE_CTRL, 0x00);
// Initiate SW reset (PLL is powered off as part of reset)
DAC3101_REGWRITE(DAC3101_SW_RST, 0x01);
// so I've got 24MHz in to PLL, I want 24.576MHz or 22.5792MHz out.
// I will always be using fractional-N (D != 0) so we must set R = 1
// PLL_CLKIN/P must be between 10 and 20MHz so we must set P = 2
// PLL_CLK = CLKIN * ((RxJ.D)/P)
// We know R = 1, P = 2.
// PLL_CLK = CLKIN * (J.D / 2)
// For 24.576MHz:
// J = 8
// D = 1920
// So PLL_CLK = 24 * (8.192/2) = 24 x 4.096 = 98.304MHz
// Then:
// NDAC = 4
// MDAC = 4
// DOSR = 128
// So:
// DAC_CLK = PLL_CLK / 4 = 24.576MHz.
// DAC_MOD_CLK = DAC_CLK / 4 = 6.144MHz.
// DAC_FS = DAC_MOD_CLK / 128 = 48kHz.
// For 22.5792MHz:
// J = 7
// D = 5264
// So PLL_CLK = 24 * (7.5264/2) = 24 x 3.7632 = 90.3168MHz
// Then:
// NDAC = 4
// MDAC = 4
// DOSR = 128
// So:
// DAC_CLK = PLL_CLK / 4 = 22.5792MHz.
// DAC_MOD_CLK = DAC_CLK / 4 = 5.6448MHz.
// DAC_FS = DAC_MOD_CLK / 128 = 44.1kHz.
/* Sample frequency dependent register settings */
if ((samFreq % 11025) == 0)
{
{
unsigned char data[1] = {0};
// MCLK = 22.5792MHz (44.1,88.2,176.4kHz)
// Set PLL J Value to 7
DAC3101_REGWRITE(DAC3101_PLL_J, 0x07);
// Set PLL D to 5264 ... (0x1490)
// Set PLL D MSB Value to 0x14
DAC3101_REGWRITE(DAC3101_PLL_D_MSB, 0x14);
// Set PLL D LSB Value to 0x90
DAC3101_REGWRITE(DAC3101_PLL_D_LSB, 0x90);
// Wait for 1ms
delay_milliseconds(1);
// Set register page to 0
DAC3101_REGWRITE(DAC3101_PAGE_CTRL, 0x00);
// Initiate SW reset (PLL is powered off as part of reset)
DAC3101_REGWRITE(DAC3101_SW_RST, 0x01);
// so I've got 24MHz in to PLL, I want 24.576MHz or 22.5792MHz out.
// I will always be using fractional-N (D != 0) so we must set R = 1
// PLL_CLKIN/P must be between 10 and 20MHz so we must set P = 2
// PLL_CLK = CLKIN * ((RxJ.D)/P)
// We know R = 1, P = 2.
// PLL_CLK = CLKIN * (J.D / 2)
// For 24.576MHz:
// J = 8
// D = 1920
// So PLL_CLK = 24 * (8.192/2) = 24 x 4.096 = 98.304MHz
// Then:
// NDAC = 4
// MDAC = 4
// DOSR = 128
// So:
// DAC_CLK = PLL_CLK / 4 = 24.576MHz.
// DAC_MOD_CLK = DAC_CLK / 4 = 6.144MHz.
// DAC_FS = DAC_MOD_CLK / 128 = 48kHz.
// For 22.5792MHz:
// J = 7
// D = 5264
// So PLL_CLK = 24 * (7.5264/2) = 24 x 3.7632 = 90.3168MHz
// Then:
// NDAC = 4
// MDAC = 4
// DOSR = 128
// So:
// DAC_CLK = PLL_CLK / 4 = 22.5792MHz.
// DAC_MOD_CLK = DAC_CLK / 4 = 5.6448MHz.
// DAC_FS = DAC_MOD_CLK / 128 = 44.1kHz.
}
else if ((samFreq % 8000) == 0)
{
// MCLK = 24.576MHz (48,96,192kHz)
// Set PLL J Value to 8
DAC3101_REGWRITE(DAC3101_PLL_J, 0x08);
// Set PLL D to 1920 ... (0x780)
// Set PLL D MSB Value to 0x07
DAC3101_REGWRITE(DAC3101_PLL_D_MSB, 0x07);
// Set PLL D LSB Value to 0x80
DAC3101_REGWRITE(DAC3101_PLL_D_LSB, 0x80);
}
else
{
//debug_printf("Unrecognised sample freq of %d in ConfigCodec\n", samFreq);
}
/* Sample frequency dependent register settings */
if ((samFreq % 11025) == 0)
{
// MCLK = 22.5792MHz (44.1,88.2,176.4kHz)
// Set PLL J Value to 7
DAC3101_REGWRITE(DAC3101_PLL_J, 0x07);
// Set PLL D to 5264 ... (0x1490)
// Set PLL D MSB Value to 0x14
DAC3101_REGWRITE(DAC3101_PLL_D_MSB, 0x14);
// Set PLL D LSB Value to 0x90
DAC3101_REGWRITE(DAC3101_PLL_D_LSB, 0x90);
delay_milliseconds(1);
// Set PLL_CLKIN = MCLK (device pin), CODEC_CLKIN = PLL_CLK (generated on-chip)
DAC3101_REGWRITE(DAC3101_CLK_GEN_MUX, 0x03);
// Set PLL P and R values and power up.
DAC3101_REGWRITE(DAC3101_PLL_P_R, 0xA1);
// Set NDAC clock divider to 4 and power up.
DAC3101_REGWRITE(DAC3101_NDAC_VAL, 0x84);
// Set MDAC clock divider to 4 and power up.
DAC3101_REGWRITE(DAC3101_MDAC_VAL, 0x84);
// Set OSR clock divider to 128.
DAC3101_REGWRITE(DAC3101_DOSR_VAL_LSB, 0x80);
// Set CLKOUT Mux to DAC_CLK
DAC3101_REGWRITE(DAC3101_CLKOUT_MUX, 0x04);
// Set CLKOUT M divider to 1 and power up.
DAC3101_REGWRITE(DAC3101_CLKOUT_M_VAL, 0x81);
// Set GPIO1 output to come from CLKOUT output.
DAC3101_REGWRITE(DAC3101_GPIO1_IO, 0x10);
// Set CODEC interface mode: I2S, 24 bit, slave mode (BCLK, WCLK both inputs).
DAC3101_REGWRITE(DAC3101_CODEC_IF, 0x20);
// Set register page to 1
DAC3101_REGWRITE(DAC3101_PAGE_CTRL, 0x01);
// Program common-mode voltage to mid scale 1.65V.
DAC3101_REGWRITE(DAC3101_HP_DRVR, 0x14);
// Program headphone-specific depop settings.
// De-pop, Power on = 800 ms, Step time = 4 ms
DAC3101_REGWRITE(DAC3101_HP_DEPOP, 0x4E);
// Program routing of DAC output to the output amplifier (headphone/lineout or speaker)
// LDAC routed to left channel mixer amp, RDAC routed to right channel mixer amp
DAC3101_REGWRITE(DAC3101_DAC_OP_MIX, 0x44);
// Unmute and set gain of output driver
// Unmute HPL, set gain = 0 db
DAC3101_REGWRITE(DAC3101_HPL_DRVR, 0x06);
// Unmute HPR, set gain = 0 dB
DAC3101_REGWRITE(DAC3101_HPR_DRVR, 0x06);
// Unmute Left Class-D, set gain = 12 dB
DAC3101_REGWRITE(DAC3101_SPKL_DRVR, 0x0C);
// Unmute Right Class-D, set gain = 12 dB
DAC3101_REGWRITE(DAC3101_SPKR_DRVR, 0x0C);
// Power up output drivers
// HPL and HPR powered up
DAC3101_REGWRITE(DAC3101_HP_DRVR, 0xD4);
// Power-up L and R Class-D drivers
DAC3101_REGWRITE(DAC3101_SPK_AMP, 0xC6);
// Enable HPL output analog volume, set = -9 dB
DAC3101_REGWRITE(DAC3101_HPL_VOL_A, 0x92);
// Enable HPR output analog volume, set = -9 dB
DAC3101_REGWRITE(DAC3101_HPR_VOL_A, 0x92);
// Enable Left Class-D output analog volume, set = -9 dB
DAC3101_REGWRITE(DAC3101_SPKL_VOL_A, 0x92);
// Enable Right Class-D output analog volume, set = -9 dB
DAC3101_REGWRITE(DAC3101_SPKR_VOL_A, 0x92);
delay_milliseconds(100);
}
else if ((samFreq % 8000) == 0)
{
// MCLK = 24.576MHz (48,96,192kHz)
// Set PLL J Value to 8
DAC3101_REGWRITE(DAC3101_PLL_J, 0x08);
// Set PLL D to 1920 ... (0x780)
// Set PLL D MSB Value to 0x07
DAC3101_REGWRITE(DAC3101_PLL_D_MSB, 0x07);
// Set PLL D LSB Value to 0x80
DAC3101_REGWRITE(DAC3101_PLL_D_LSB, 0x80);
}
else
{
//debug_printf("Unrecognised sample freq of %d in ConfigCodec\n", samFreq);
}
// Power up DAC
// Set register page to 0
DAC3101_REGWRITE(DAC3101_PAGE_CTRL, 0x00);
// Power up DAC channels and set digital gain
// Powerup DAC left and right channels (soft step enabled)
DAC3101_REGWRITE(DAC3101_DAC_DAT_PATH, 0xD4);
// DAC Left gain = 0dB
DAC3101_REGWRITE(DAC3101_DACL_VOL_D, 0x00);
// DAC Right gain = 0dB
DAC3101_REGWRITE(DAC3101_DACR_VOL_D, 0x00);
// Unmute digital volume control
// Unmute DAC left and right channels
DAC3101_REGWRITE(DAC3101_DAC_VOL, 0x00);
delay_milliseconds(1);
// Set PLL_CLKIN = MCLK (device pin), CODEC_CLKIN = PLL_CLK (generated on-chip)
DAC3101_REGWRITE(DAC3101_CLK_GEN_MUX, 0x03);
// Set PLL P and R values and power up.
DAC3101_REGWRITE(DAC3101_PLL_P_R, 0xA1);
// Set NDAC clock divider to 4 and power up.
DAC3101_REGWRITE(DAC3101_NDAC_VAL, 0x84);
// Set MDAC clock divider to 4 and power up.
DAC3101_REGWRITE(DAC3101_MDAC_VAL, 0x84);
// Set OSR clock divider to 128.
DAC3101_REGWRITE(DAC3101_DOSR_VAL_LSB, 0x80);
// Set CLKOUT Mux to DAC_CLK
DAC3101_REGWRITE(DAC3101_CLKOUT_MUX, 0x04);
// Set CLKOUT M divider to 1 and power up.
DAC3101_REGWRITE(DAC3101_CLKOUT_M_VAL, 0x81);
// Set GPIO1 output to come from CLKOUT output.
DAC3101_REGWRITE(DAC3101_GPIO1_IO, 0x10);
// Set CODEC interface mode: I2S, 24 bit, slave mode (BCLK, WCLK both inputs).
DAC3101_REGWRITE(DAC3101_CODEC_IF, 0x20);
// Set register page to 1
DAC3101_REGWRITE(DAC3101_PAGE_CTRL, 0x01);
// Program common-mode voltage to mid scale 1.65V.
DAC3101_REGWRITE(DAC3101_HP_DRVR, 0x14);
// Program headphone-specific depop settings.
// De-pop, Power on = 800 ms, Step time = 4 ms
DAC3101_REGWRITE(DAC3101_HP_DEPOP, 0x4E);
// Program routing of DAC output to the output amplifier (headphone/lineout or speaker)
// LDAC routed to left channel mixer amp, RDAC routed to right channel mixer amp
DAC3101_REGWRITE(DAC3101_DAC_OP_MIX, 0x44);
// Unmute and set gain of output driver
// Unmute HPL, set gain = 0 db
DAC3101_REGWRITE(DAC3101_HPL_DRVR, 0x06);
// Unmute HPR, set gain = 0 dB
DAC3101_REGWRITE(DAC3101_HPR_DRVR, 0x06);
// Unmute Left Class-D, set gain = 12 dB
DAC3101_REGWRITE(DAC3101_SPKL_DRVR, 0x0C);
// Unmute Right Class-D, set gain = 12 dB
DAC3101_REGWRITE(DAC3101_SPKR_DRVR, 0x0C);
// Power up output drivers
// HPL and HPR powered up
DAC3101_REGWRITE(DAC3101_HP_DRVR, 0xD4);
// Power-up L and R Class-D drivers
DAC3101_REGWRITE(DAC3101_SPK_AMP, 0xC6);
// Enable HPL output analog volume, set = -9 dB
DAC3101_REGWRITE(DAC3101_HPL_VOL_A, 0x92);
// Enable HPR output analog volume, set = -9 dB
DAC3101_REGWRITE(DAC3101_HPR_VOL_A, 0x92);
// Enable Left Class-D output analog volume, set = -9 dB
DAC3101_REGWRITE(DAC3101_SPKL_VOL_A, 0x92);
// Enable Right Class-D output analog volume, set = -9 dB
DAC3101_REGWRITE(DAC3101_SPKR_VOL_A, 0x92);
delay_milliseconds(100);
// Power up DAC
// Set register page to 0
DAC3101_REGWRITE(DAC3101_PAGE_CTRL, 0x00);
// Power up DAC channels and set digital gain
// Powerup DAC left and right channels (soft step enabled)
DAC3101_REGWRITE(DAC3101_DAC_DAT_PATH, 0xD4);
// DAC Left gain = 0dB
DAC3101_REGWRITE(DAC3101_DACL_VOL_D, 0x00);
// DAC Right gain = 0dB
DAC3101_REGWRITE(DAC3101_DACR_VOL_D, 0x00);
// Unmute digital volume control
// Unmute DAC left and right channels
DAC3101_REGWRITE(DAC3101_DAC_VOL, 0x00);
// Shutdown
//i_i2c[0].shutdown();
}
} /* par */
}
//These are here just to silence compiler warnings

9
examples/xua_lite_example/src/app_xua_lite.xc
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@@ -10,6 +10,10 @@
#include "i2c.h"
#include "gpio.h"
#define DEBUG_UNIT XUA_APP
#define DEBUG_PRINT_ENABLE_XUA_APP 1
#include "debug_print.h"
// Port declarations. Note, the defines come from the xn file
on tile[0]: buffered out port:32 p_i2s_dac[] = {XS1_PORT_1M}; //DAC
on tile[0]: buffered in port:32 p_i2s_adc[] = {XS1_PORT_1N}; //Unused currently
@@ -17,7 +21,7 @@ on tile[0]: buffered out port:32 p_lrclk = XS1_PORT_1O; //I2S Bit-clo
on tile[0]: out port p_bclk = XS1_PORT_1P; //I2S L/R-clock
// Master clock for the audio IO tile
on tile[0]: in port p_mclk_in = XS1_PORT_1A;
on tile[0]: in port p_mclk_in = XS1_PORT_1K;
// Resources for USB feedback
on tile[0]: in port p_for_mclk_count= XS1_PORT_16A; // Extra port for counting master clock ticks
@@ -35,6 +39,7 @@ on tile[1]: port p_sda = XS1_PORT_1D;
// Clock-block declarations
clock clk_audio_bclk = on tile[0]: XS1_CLKBLK_2; // Bit clock
clock clk_audio_mclk = on tile[0]: XS1_CLKBLK_3; // Master clock
//XUD uses XS1_CLKBLK_4, XS1_CLKBLK_5
// Endpoint type tables - informs XUD what the transfer types for each Endpoint in use and also
// if the endpoint wishes to be informed of USB bus resets
@@ -79,7 +84,7 @@ int main()
XUD_Main(c_ep_out, 2, c_ep_in, 3,
c_sof, epTypeTableOut, epTypeTableIn,
null, null, -1 ,
XUD_SPEED_FS, XUD_PWR_BUS);
(AUDIO_CLASS == 1) ? XUD_SPEED_FS : XUD_SPEED_HS, XUD_PWR_BUS);
// Endpoint 0 core from lib_xua
// Note, since we are not using many features we pass in null for quite a few params..

11
examples/xua_lite_example/src/audio_hub.xc
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@@ -2,11 +2,16 @@
#include "i2c.h"
#include "gpio.h"
#include "xua.h"
#define DEBUG_UNIT XUA_AUDIO_HUB
#define DEBUG_PRINT_ENABLE_XUA_AUDIO_HUB 1
#include "debug_print.h"
void AudioHwConfigure(unsigned samFreq, client i2c_master_if i_i2c);
[[distributable]]
void AudioHub(server i2s_frame_callback_if i2s,
chanend c_aud,
client i2c_master_if i2c,
client i2c_master_if i_i2c,
client output_gpio_if dac_reset)
{
int32_t samples[8] = {0}; // Array used for looping back samples
@@ -25,7 +30,8 @@ void AudioHub(server i2s_frame_callback_if i2s,
// Take CODECs out of reset
dac_reset.output(1);
//reset_codecs(i2c);
AudioHwConfigure(DEFAULT_FREQ, i_i2c);
debug_printf("I2S init\n");
break;
case i2s.receive(size_t n_chans, int32_t in_samps[n_chans]):
@@ -38,6 +44,7 @@ void AudioHub(server i2s_frame_callback_if i2s,
case i2s.restart_check() -> i2s_restart_t restart:
restart = I2S_NO_RESTART; // Keep on looping
debug_printf("I2S restart\n");
break;
}
}

22
examples/xua_lite_example/src/xua_buffer.xc
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@@ -2,8 +2,10 @@
#include "xua_commands.h"
#include "xud.h"
#include "testct_byref.h"
#define DEBUG_UNIT XUA_LITE_BUFFER
#define DEBUG_PRINT_ENABLE_XUA_LITE_BUFFER 1
#include "debug_print.h"
#include "xua_conf.h"
#include "xua.h"
//#include "fifo_impl.h" //xua_conf.h must be included before hand so that we have FIFO sizes
//Currently only single frequency supported
@@ -98,6 +100,8 @@ void XUA_Buffer_lite(chanend c_aud_out, chanend c_feedback, chanend c_aud_in, ch
unsigned char buffer_aud_out[OUT_AUDIO_BUFFER_SIZE_BYTES];
unsigned char buffer_aud_in[IN_AUDIO_BUFFER_SIZE_BYTES];
unsigned char buffer_feedback[4];
unsigned in_subslot_size = (AUDIO_CLASS == 1) ? FS_STREAM_FORMAT_INPUT_1_SUBSLOT_BYTES : HS_STREAM_FORMAT_INPUT_1_SUBSLOT_BYTES;
unsigned out_subslot_size = (AUDIO_CLASS == 1) ? FS_STREAM_FORMAT_OUTPUT_1_SUBSLOT_BYTES : HS_STREAM_FORMAT_OUTPUT_1_SUBSLOT_BYTES;
@@ -107,7 +111,9 @@ void XUA_Buffer_lite(chanend c_aud_out, chanend c_feedback, chanend c_aud_in, ch
unsigned tmp;
XUD_ep ep_aud_out = XUD_InitEp(c_aud_out);
XUD_ep ep_feedback = XUD_InitEp(c_feedback);
XUD_ep ep_aud_in = XUD_InitEp(c_aud_in);
unsigned num_samples_received_from_host = 0;
@@ -116,6 +122,7 @@ void XUA_Buffer_lite(chanend c_aud_out, chanend c_feedback, chanend c_aud_in, ch
XUD_SetReady_OutPtr(ep_aud_out, (unsigned)buffer_aud_out);
XUD_SetReady_InPtr(ep_aud_in, (unsigned)buffer_aud_in, num_samples_to_send_to_host);
XUD_SetReady_InPtr(ep_feedback, (unsigned)buffer_feedback, 4);
// printintln(OUT_AUDIO_BUFFER_SIZE_BYTES);
// printintln(MAX_OUT_SAMPLES_PER_SOF_PERIOD);
@@ -245,19 +252,22 @@ void XUA_Buffer_lite(chanend c_aud_out, chanend c_feedback, chanend c_aud_in, ch
outstanding_samples_to_host += num_samples_received_from_host;
int samples[MAX_OUT_SAMPLES_PER_SOF_PERIOD];
unpack_buff_to_samples(buffer_aud_out, num_samples_received_from_host, out_subslot_size, samples);
//Push into fifo for ASRC
//else debug_printf("Push\n");
//Tell ASRC manager what we have just sent
outuint(c_aud_host, num_samples_received_from_host); //We assume this will not block and other side always consumes
num_samples_to_send_to_host = inuint(c_aud_host); //get number of return samples for sending back to host
//outuint(c_aud_host, num_samples_received_from_host); //We assume this will not block and other side always consumes
//num_samples_to_send_to_host = inuint(c_aud_host); //get number of return samples for sending back to host
//Mark EP as ready for next frame from host
XUD_SetReady_OutPtr(ep_aud_out, (unsigned)buffer_aud_out);
break;
//Send feedback
case XUD_SetData_Select(c_feedback, ep_feedback, result):
debug_printf("ep_feedback\n");
XUD_SetReady_InPtr(ep_feedback, (unsigned)buffer_feedback, 4);
break;
//Send samples to host
case XUD_SetData_Select(c_aud_in, ep_aud_in, result):
//debug_printf("sent data\n");

18
lib_xua/src/core/endpoint0/xua_endpoint0.c
View File

@@ -297,9 +297,25 @@ void XUA_Endpoint0(chanend c_ep0_out, chanend c_ep0_in, chanend c_audioControl,
while(1)
{
#if XUA_LITE
unsigned char sbuffer[120];
unsigned length;
//XUD_Result_t result = XUD_GetSetupBuffer(ep0_out, sbuffer, &length); //Flattened from xud_device
XUD_Result_t result = XUD_GetSetupData(ep0_out, sbuffer, &length);//Flattened from XUD_EpFunctions.xc
//Next step:
//void XUD_GetSetupData_Select(chan c,XUD_ep e_out, unsigned &length, XUD_Result_t &result);
if (result == XUD_RES_OKAY)
{
/* Parse data buffer end populate SetupPacket struct */
USB_ParseSetupPacket(sbuffer, &sp);
}
#else
/* Returns XUD_RES_OKAY for success, XUD_RES_RST for bus reset */
XUD_Result_t result = USB_GetSetupPacket(ep0_out, ep0_in, &sp);
#endif
if (result == XUD_RES_OKAY)
{
result = XUD_RES_ERR;