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@@ -1,4 +1,4 @@
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// Copyright 2016-2021 XMOS LIMITED.
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// Copyright 2016-2022 XMOS LIMITED.
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// This Software is subject to the terms of the XMOS Public Licence: Version 1.
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#ifdef HARDWARE
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@@ -8,7 +8,7 @@
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#include "devicedefines.h"
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#include <platform.h>
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#include "gpio_access.h"
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#include "i2c_shared.h"
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#include "i2c.h"
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#include "cs4384.h"
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#include "cs5368.h"
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#include "cs2100.h"
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@@ -25,16 +25,10 @@
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on tile[0] : out port p_gpio = XS1_PORT_8C;
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#ifndef IAP
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/* If IAP not enabled, i2c ports not declared - still needs for DAC config */
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on tile [0] : struct r_i2c r_i2c = {XS1_PORT_4A};
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#else
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extern struct r_i2c r_i2c;
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#endif
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port p_i2c = on tile[0]:PORT_I2C;
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#define DAC_REGWRITE(reg, val) {data[0] = val; i2c_shared_master_write_reg(r_i2c, CS4384_I2C_ADDR, reg, data, 1);}
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#define DAC_REGREAD(reg, val) {i2c_shared_master_read_reg(r_i2c, CS4384_I2C_ADDR, reg, val, 1);}
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#define ADC_REGWRITE(reg, val) {data[0] = val; i2c_shared_master_write_reg(r_i2c, CS5368_I2C_ADDR, reg, data, 1);}
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#define DAC_REGWRITE(reg, val) {result = i2c.write_reg(CS4384_I2C_ADDR, reg, val);}
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#define ADC_REGWRITE(reg, val) {result = i2c.write_reg(CS5368_I2C_ADDR, reg, val);}
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#ifdef USE_FRACTIONAL_N
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@@ -45,14 +39,15 @@ extern struct r_i2c r_i2c;
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#define PLL_SYNC_FREQ 300
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#endif
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#define CS2100_REGREAD(reg, data) {data[0] = 0xAA; i2c_master_read_reg(CS2100_I2C_DEVICE_ADDR, reg, data, 1, r_i2c);}
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#define CS2100_REGREAD_ASSERT(reg, data, expected) {data[0] = 0xAA; i2c_master_read_reg(CS2100_I2C_DEVICE_ADDR, reg, data, 1, r_i2c); assert(data[0] == expected);}
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#define CS2100_REGWRITE(reg, val) {data[0] = val; i2c_master_write_reg(CS2100_I2C_DEVICE_ADDR, reg, data, 1, r_i2c);}
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#define CS2100_REGREAD(reg, data) {data[0] = i2c.read_reg(CS2100_I2C_DEVICE_ADDR, reg, result);}
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#define CS2100_REGREAD_ASSERT(reg, data, expected) {data[0] = i2c.read_reg(CS2100_I2C_DEVICE_ADDR, reg, result); assert(data[0] == expected);}
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#define CS2100_REGWRITE(reg, val) {result = i2c.write_reg(CS2100_I2C_DEVICE_ADDR, reg, val);}
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/* Init of CS2100 */
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void PllInit(void)
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void PllInit(client interface i2c_master_if i2c)
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{
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unsigned char data[1] = {0};
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i2c_regop_res_t result;
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#if XCORE_200_MC_AUDIO_HW_VERSION < 2
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/* Enable init */
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@@ -73,12 +68,15 @@ void PllInit(void)
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CS2100_REGREAD_ASSERT(CS2100_GLOBAL_CONFIG, data, 0x01);
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CS2100_REGREAD_ASSERT(CS2100_FUNC_CONFIG_1, data, 0x08);
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CS2100_REGREAD_ASSERT(CS2100_FUNC_CONFIG_2, data, 0x00);
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i2c.shutdown();
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}
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/* Setup PLL multiplier */
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void PllMult(unsigned output, unsigned ref)
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void PllMult(unsigned output, unsigned ref, client interface i2c_master_if i2c)
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{
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unsigned char data[1] = {0};
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i2c_regop_res_t result;
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/* PLL expects 12:20 format, convert output and ref to 12:20 */
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/* Shift up the dividend by 12 to retain format... */
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@@ -120,9 +118,6 @@ void AudioHwInit(chanend ?c_codec)
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start_clock(clk_pll_sync);
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#endif
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/* Init the i2c module */
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i2c_shared_master_init(r_i2c);
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/* Assert reset to ADC and DAC */
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set_gpio(P_GPIO_DAC_RST_N, 0);
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set_gpio(P_GPIO_ADC_RST_N, 0);
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@@ -143,7 +138,12 @@ void AudioHwInit(chanend ?c_codec)
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set_gpio(P_GPIO_PLL_SEL, 1);
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/* Initialise external PLL */
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PllInit();
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i2c_master_if i2c[1];
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par
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{
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i2c_master_single_port(i2c, 1, p_i2c, 10, 0, 1, 0);
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PllInit(i2c[0]);
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}
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#endif
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#ifdef IAP
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@@ -155,10 +155,11 @@ void AudioHwInit(chanend ?c_codec)
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/* Configures the external audio hardware for the required sample frequency.
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* See gpio.h for I2C helper functions and gpio access
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*/
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void AudioHwConfig(unsigned samFreq, unsigned mClk, chanend ?c_codec, unsigned dsdMode,
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unsigned sampRes_DAC, unsigned sampRes_ADC)
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void AudioHwConfig2(unsigned samFreq, unsigned mClk, chanend ?c_codec, unsigned dsdMode,
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unsigned sampRes_DAC, unsigned sampRes_ADC, client interface i2c_master_if i2c)
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{
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unsigned char data[1] = {0};
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unsigned char data[1] = {0};
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i2c_regop_res_t result;
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/* Put ADC and DAC into reset */
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set_gpio(P_GPIO_ADC_RST_N, 0);
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@@ -167,7 +168,7 @@ void AudioHwConfig(unsigned samFreq, unsigned mClk, chanend ?c_codec, unsigned d
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/* Set master clock select appropriately */
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#if defined(USE_FRACTIONAL_N)
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/* Configure external fractional-n clock multiplier for 300Hz -> mClkFreq */
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PllMult(mClk, PLL_SYNC_FREQ);
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PllMult(mClk, PLL_SYNC_FREQ, i2c);
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#endif
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/* Allow some time for mclk to lock and MCLK to stabilise - this is important to avoid glitches at start of stream */
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{
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@@ -365,8 +366,20 @@ void AudioHwConfig(unsigned samFreq, unsigned mClk, chanend ?c_codec, unsigned d
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DAC_REGWRITE(CS4384_MODE_CTRL, 0b10000000);
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}
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#endif
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i2c.shutdown();
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return;
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}
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//:
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void AudioHwConfig(unsigned samFreq, unsigned mClk, chanend ?c_codec, unsigned dsdMode,
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unsigned sampRes_DAC, unsigned sampRes_ADC)
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{
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i2c_master_if i2c[1];
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par
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{
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i2c_master_single_port(i2c, 1, p_i2c, 10, 0, 1, 0);
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AudioHwConfig2(samFreq, mClk, c_codec, dsdMode, sampRes_DAC, sampRes_ADC, i2c[0]);
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}
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}
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#endif
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