Vergil_Wong/lib_xua
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Further removed of XS1 support items

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This commit is contained in:
xross
2021-10-18 17:05:35 +01:00
parent 32af5b7b20
commit 2bbebc0a39
3 changed files with 0 additions and 32 deletions
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5
lib_xua/src/core/buffer/decouple/interrupt.h
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@@ -72,13 +72,8 @@
//int ksp_enter, ksp_exit, r11_store;
#if defined(__XS2A__) || defined(__XS3A__)
#define ISSUE_MODE_SINGLE ".issue_mode single\n"
#define ISSUE_MODE_DUAL ".issue_mode dual\n"
#else
#define ISSUE_MODE_SINGLE
#define ISSUE_MODE_DUAL
#endif
#define do_interrupt_handler(f,args) \
asm(ISSUE_MODE_SINGLE\

2
lib_xua/src/core/mixer/fastmix.S
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@@ -65,8 +65,6 @@ doMix##i##: ;\
retsp 0x0; \
#if(MAX_MIX_COUNT > 0)
DOMIX_TOP(0)
#include "repeat.h"

25
lib_xua/src/core/ports/audioports.xc
View File

@@ -62,37 +62,12 @@ unsigned int divide, unsigned curSamFreq)
}
#endif
#if defined(__XS2A__) || defined(__XS3A__)
unsafe
{
/* Clock bitclock clock block from master clock pin (divided) */
configure_clock_src_divide(clk_audio_bclk, (port) p_mclk_in, (divide/2));
configure_port_clock_output(p_bclk, clk_audio_bclk);
}
#else
#error XS1 no longer supported in audio core
/* For a divide of one (i.e. bitclock == master-clock) BClk is set to clock_output mode.
* In this mode it outputs an edge clock on every tick of itsassociated clock_block.
*
* For all other divides, BClk is clocked by the master clock and data
* will be output to p_bclk to generate the bit clock.
*/
if (divide == 1) /* e.g. 176.4KHz from 11.2896 */
{
configure_port_clock_output(p_bclk, clk_audio_mclk);
/* Generate bit clock block straight from mclk */
configure_clock_src(clk_audio_bclk, p_mclk_in);
}
else
{
/* bit clock port from master clock clock-clock block */
configure_out_port_no_ready(p_bclk, clk_audio_mclk, 0);
/* Generate bit clock block from pin */
configure_clock_src(clk_audio_bclk, p_bclk);
}
#endif
if(!isnull(p_lrclk))
{