Vergil_Wong/lib_xua
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

- test_sync_clk_basic and test_sync_clk_plugin now run at FS & HS

Browse Source 
- test_sync_clk_plugin marked as known failure (now fails as expected for HS and FS)
This commit is contained in:
xross
2022-08-04 19:54:29 +01:00
parent 3a9f2fff3a
commit 5690442a4b
7 changed files with 89 additions and 50 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
tests/conftest.py
View File

@@ -8,7 +8,7 @@ def pytest_addoption(parser):
default=False,
help="Run tests with instruction tracing",
)
parser.addoption(
"--enablevcdtracing",
action="store_true",
@@ -16,6 +16,7 @@ def pytest_addoption(parser):
help="Run tests with vcd tracing",
)
@pytest.fixture
def options(request):
yield request.config.option

19
tests/test_sync_clk_basic.py
View File

@@ -10,11 +10,11 @@ def test_file(request):
return str(request.node.fspath)
def do_test(test_file, options, capfd):
def do_test(bus_speed, test_file, options, capfd):
testname, _ = os.path.splitext(os.path.basename(test_file))
binary = f"{testname}/bin/{testname}.xe"
binary = f"{testname}/bin/{bus_speed}/{testname}_{bus_speed}.xe"
tester = testers.ComparisonTester(open("pass.expect"))
@@ -25,7 +25,6 @@ def do_test(test_file, options, capfd):
+ "-port tile[0] XS1_PORT_1P 1 0 -port tile[0] XS1_PORT_1L 1 0 "
+ "-port tile[0] XS1_PORT_1A 1 0 -port tile[0] XS1_PORT_1B 1 0 "
)
max_cycles = 15000000 # enough to reach the 10 skip + 100 test in sim at 48kHz
@@ -37,13 +36,21 @@ def do_test(test_file, options, capfd):
loopback_args,
]
result = Pyxsim.run_on_simulator(binary, tester=tester, simargs=simargs, capfd=capfd, instTracing=options.enabletracing, vcdTracing=options.enablevcdtracing)
result = Pyxsim.run_on_simulator(
binary,
tester=tester,
simargs=simargs,
capfd=capfd,
instTracing=options.enabletracing,
vcdTracing=options.enablevcdtracing,
)
return result
def test_sync_clk_basic(test_file, options, capfd):
@pytest.mark.parametrize("bus_speed", ["FS", "HS"])
def test_sync_clk_basic(bus_speed, test_file, options, capfd):
result = do_test(test_file, options, capfd)
result = do_test(bus_speed, test_file, options, capfd)
assert result

8
tests/test_sync_clk_basic/Makefile
View File

@@ -1,7 +1,13 @@
TEST_FLAGS ?=
XCC_FLAGS = -O3 -g -DXUD_CORE_CLOCK=600 -save-temps -DUSB_TILE=tile[0] -DLOCAL_CLOCK_INCREMENT=10000 -DLOCAL_CLOCK_MARGIN=100 $(TEST_FLAGS)
XCC_FLAGS_HS = -O3 -g -DXUD_CORE_CLOCK=600 -save-temps -DUSB_TILE=tile[0] -DLOCAL_CLOCK_INCREMENT=10000 -DLOCAL_CLOCK_MARGIN=100 \
-DBUS_SPEED=2 \
$(TEST_FLAGS)
XCC_FLAGS_FS = -O3 -g -DXUD_CORE_CLOCK=600 -save-temps -DUSB_TILE=tile[0] -DLOCAL_CLOCK_INCREMENT=10000 -DLOCAL_CLOCK_MARGIN=100 \
-DBUS_SPEED=1 \
$(TEST_FLAGS)
TARGET = test_xs3_600.xn

83
tests/test_sync_clk_basic/src/main.xc
View File

@@ -1,30 +1,44 @@
// Copyright 2022 XMOS LIMITED.
// This Software is subject to the terms of the XMOS Public Licence: Version 1.
/* Simples test to ensure reference clock to CS2100 device continues when SOF clock not available
* Note, this test uses "nice" numbers and it doesn't check for graceful change over from internal to SOF clock
/* Simple test to ensure reference clock to CS2100 device continues when SOF clock not available
* Note, this test uses "nice" numbers (i.e. MISSIG_SOFS %8 == 0) and therefore doesn't check
* for a graceful change over from internal to SOF clock
*/
#include "platform.h"
#include "xua.h"
#include "uac_hwresources.h"
#include "print.h"
#include "xud.h"
#define EP_COUNT_IN 3
#define EP_COUNT_OUT 3
#define EP_COUNT_IN (3)
#define EP_COUNT_OUT (3)
out port p_pll_ref = XS1_PORT_1A;
in port p_off_mclk = XS1_PORT_1M;
in port p_pll_loop = XS1_PORT_1B; /* Note, this is externally looped back using the loopback plugin */
out port p_pll_ref = XS1_PORT_1A;
in port p_off_mclk = XS1_PORT_1M;
in port p_pll_loop = XS1_PORT_1B; /* Note, this is externally looped back using the loopback plugin */
/* Purely for debug/viewing on VCD */
out port p_test = XS1_PORT_1C;
out port p_test0 = XS1_PORT_1C;
out port p_test1 = XS1_PORT_1D;
#ifndef BUS_SPEED
#error BUS_SPEED should be defined
#endif
/* To speed this test up we divide all delays by 10. This is also the case for the delays in the clock generation code */
#define SOF_PERIOD_TICKS (12500/10)
#if(BUS_SPEED == 2) // XUD_SPEED_HS
#define SOF_PERIOD_TICKS (12500/10)
#define SOF_DIVIDE (1)
#else
#define SOF_PERIOD_TICKS ((12500*8)/10)
#define SOF_DIVIDE (8)
#endif
#ifndef MISSING_SOFS
#define MISSING SOFS (8)
#ifndef MISSING_SOF_PERIOD
/* By default skip a whole number of SOF periods (easy case)
* Note, app_test_sync_plugin/Makefiles sets this to something more nasty */
#define MISSING_SOF_PERIOD (8 * SOF_PERIOD_TICKS)
#endif
void exit(int);
@@ -45,18 +59,19 @@ void AudioHwInit()
return;
}
void AudioHwConfig(unsigned samFreq, unsigned mClk, unsigned dsdMode,
unsigned sampRes_DAC, unsigned sampRes_ADC)
void AudioHwConfig(unsigned samFreq, unsigned mClk, unsigned dsdMode, unsigned sampRes_DAC, unsigned sampRes_ADC)
{
return;
}
void driveSofs(chanend c_sof, int count)
{
static int sof = 0;
static int frame = 0;
/* For HS frame should only increment every 8 SOFs, but this is a "dont care" */
for(int i = 0; i < count; i++)
{
outuint(c_sof, sof++);
outuint(c_sof, frame++);
delay(SOF_PERIOD_TICKS);
}
}
@@ -66,11 +81,12 @@ void fake_xud(chanend c_out[], chanend c_in[], chanend c_sof)
timer t;
unsigned time;
p_test <: 1;
/* Makes traces a bit nicer to look at */
t :> time;
t when timerafter(SOF_PERIOD_TICKS * 2) :> int x;
p_test0 <: 1;
/* Endpoint type tables */
XUD_EpType epTypeTableOut[EP_COUNT_OUT] = {XUD_EPTYPE_CTL, XUD_EPTYPE_ISO, XUD_EPTYPE_DIS};
@@ -78,38 +94,48 @@ void fake_xud(chanend c_out[], chanend c_in[], chanend c_sof)
SetupEndpoints(c_out, EP_COUNT_OUT, c_in, EP_COUNT_IN, epTypeTableOut, epTypeTableIn);
driveSofs(c_sof, 32);
driveSofs(c_sof, 32/SOF_DIVIDE);
p_test <: 0;
p_test0 <: 0;
/* Sim missing SOFs */
delay(SOF_PERIOD_TICKS*MISSING_SOFS);
delay(MISSING_SOF_PERIOD);
p_test <: 1;
p_test0 <: 1;
driveSofs(c_sof, 16);
driveSofs(c_sof, 16/SOF_DIVIDE);
p_test0 <: 0;
delay(MISSING_SOF_PERIOD);
p_test0 <: 1;
driveSofs(c_sof, 16/SOF_DIVIDE);
p_test0 <: 0;
p_test <: 0;
}
extern XUD_BusSpeed_t g_curUsbSpeed;
#define MARGIN (1500/10)
#define EXPECTED_PERIOD (100000/10) // Test runs as HS - so 8 * 125000
#define EXPECTED_PERIOD (100000/10)
void checker()
{
timer t;
unsigned t0, t1;
unsigned x = 0;
int fail = 0;
p_test1 <: 1;
p_pll_loop when pinseq(1) :> x;
p_pll_loop when pinseq(0) :> x;
p_pll_loop when pinseq(1) :> x;
for(int i = 0; i < 8; i++)
for(int i = 0; i < 12; i++)
{
p_pll_loop when pinsneq(x) :> x;
t :> t0;
@@ -135,6 +161,8 @@ void checker()
if(!fail)
printstrln("PASS");
p_test1 <: 0;
exit(0);
}
@@ -153,7 +181,8 @@ int main()
PllRefPinTask(i_pll_ref, p_pll_ref);
{
g_curUsbSpeed = XUD_SPEED_HS;
g_curUsbSpeed = BUS_SPEED;
XUA_Buffer_Ep(c_out[1], /* USB Audio Out*/
c_in[1], /* USB Audio In */
c_sof, c_aud_ctl, p_off_mclk, i_pll_ref

19
tests/test_sync_clk_plugin.py
View File

@@ -1,19 +1,10 @@
import pytest
import Pyxsim
from Pyxsim import testers
import os
import sys
from test_sync_clk_basic import do_test
from test_sync_clk_basic import test_file
@pytest.fixture()
def test_file(request):
return str(request.node.fspath)
def test_sync_clk_plugin(test_file, options, capfd):
#pytest.xfail("This is a known failure due to issue #275")
result = do_test(test_file, options, capfd)
@pytest.mark.parametrize("bus_speed", ["FS", "HS"])
def test_sync_clk_plugin(bus_speed, test_file, options, capfd):
pytest.xfail("This is a known failure due to issue #275")
result = do_test(bus_speed, test_file, options, capfd)
assert result

3
tests/test_sync_clk_plugin/Makefile
View File

@@ -1,3 +1,4 @@
TEST_FLAGS = -DMISSING_SOFS=4
TEST_FLAGS = -DMISSING_SOF_PERIOD=7500
include ../test_sync_clk_basic/Makefile

4
tests/test_sync_clk_plugin/src/main.xc
View File

@@ -1,2 +1,6 @@
/* This tests for a smooth transition from internal to SOF clock.
* Unlike test_sync_clk_basic it does not use a "nice" value for MISSING_SOFS
*/
#include "../test_sync_clk_basic/src/main.xc"