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Fixed up null USB reset port but not null USB clock. This is for case when UserReset is used to reset USB phy (L1 iOS board has USB phy rst on shiftreg

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Ross Owen
2013-12-19 11:55:34 +00:00
parent 7fe8f1bbce
commit 855ba6b83f
1 changed files with 6 additions and 4 deletions
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10
module_usb_audio/main.xc
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@@ -138,16 +138,18 @@ on tile[AUDIO_IO_TILE] : clock clk_mst_spd = XS1_CLKBLK_1;
#endif
/* L Series needs a port to use for USB reset */
#if defined(ARCH_L) || defined(ARCH_G)
#ifdef PORT_USB_RESET
#if (defined(ARCH_L) || defined(ARCH_G)) && defined(PORT_USB_RESET)
/* This define is checked since it could be on a shift reg or similar */
on tile[XUD_TILE] : out port p_usb_rst = PORT_USB_RESET;
#else
/* Reset port not required for U series due to built in Phy */
#define p_usb_rst null
#endif
#if defined (ARCH_L) || defined(ARCH_G)
/* L Series also needs a clock for this port */
on tile[XUD_TILE] : clock clk = XS1_CLKBLK_4;
#else
/* Reset port not required for SU1 due to built in Phy */
#define p_usb_rst null
#define clk null
#endif