Initial documentation covering sw_pll

lib_xua/doc/rst/arch.rst

@@ -54,7 +54,9 @@ In addition :ref:`usb_audio_optional_components` shows optional components that
  * - Clockgen
    - Drives an external frequency generator (PLL) and manages
      changes between internal clocks and external clocks arising
-     from digital input.
+     from digital input. on xCORE-AI Clockgen may also work in
+     conjunction with lib_sw_pll to produce a local clock from 
+     the XCORE which is locked to the incoming digital stream.
  * - MIDI
    - Outputs and inputs MIDI over a serial UART interface.
 

lib_xua/doc/rst/feat_spdif_rx.rst

@@ -29,10 +29,11 @@ The S/PDIF receiver should be called on the appropriate tile::
 With the steps above an S/PDIF stream can be captured by the xCORE. To be functionally useful the audio
 master clock must be able to synchronise to this external digital stream. Additionally, the host can be 
 notified regarding changes in the validity of this stream, it's frequency etc. To synchronise to external 
-streams the codebase assumes the use of an external Cirrus Logic CS2100 device.
+streams the codebase assumes the use of an external Cirrus Logic CS2100 device or lib_sw_pll on xCORE-AI designs.
 
-The ``ClockGen()`` task from ``lib_xua`` provides the reference signal to the CS2100 device and also handles
-recording of clock validity etc. See :ref:`usb_audio_sec_clock_recovery` for full details regarding ``ClockGen()``.
+The ``ClockGen()`` task from ``lib_xua`` provides the reference signal to the CS2100 device or timing information
+to lib_sw_pll and also handles recording of clock validity etc.
+See :ref:`usb_audio_sec_clock_recovery` for full details regarding ``ClockGen()``.
 
 It also provides a small FIFO for S/PDIF samples before they are forwarded to the ``AudioHub`` core.
 As such it requires to be inserted in the communication path between the S/PDIF receiver and the 

lib_xua/doc/rst/hw.rst

@@ -52,11 +52,11 @@ Three methods of generating an audio master clock are provided on the board:
 
     * A Skyworks Si5351B PLL device. The Si5351 is an I2C configurable clock generator that is ideally suited for replacing crystals, crystal oscillators, VCXOs, phase-locked loops (PLLs), and fanout buffers.
 
-    * xCORE.ai devices are equipped with a secondary (or 'application') PLL which can be used to generate audio clocks
+    * xCORE.ai devices are equipped with a secondary (or 'application') PLL which can be used to generate fixed audio clocks or recover external clocks using lib_sw_pll.
 
 Selection between these methods is done via writing to bits 6 and 7 of PORT 8D on tile[0]. 
 
-Either the locally generated clock (from the PL611) or the recovered low jitter clock (from the CS2100) may be selected to clock the audio stages; the xCORE-200, the ADC/DAC and Digital output stages. Selection is controlled via an additional I/O, bit 5 of PORT 8C, see :ref:`hw_316_ctrlport`.
+Either the locally generated clock (from the PL611) or the recovered low jitter clock (from the CS2100) may be selected to clock the audio stages; the xCORE-AI, the ADC/DAC and Digital output stages. Selection is controlled via an additional I/O, bit 5 of PORT 8C, see :ref:`hw_316_ctrlport`.
 
 .. _hw_316_ctrlport:
 

lib_xua/doc/rst/opt_spdif_rx.rst

@@ -33,8 +33,8 @@ This must be a 1-bit port, for example::
 
     <Port Location="XS1_PORT_1A"  Name="PORT_SPDIF_IN"/>
 
-When S/PDIF receive is enabled the codebase expects to drive a synchronisation signal to an external 
-Cirrus Logic CS2100 device for master-clock generation.
+When S/PDIF receive is enabled the codebase expects to either drive a synchronisation signal to an external 
+Cirrus Logic CS2100 device or use lib_swp_pll (xCORE-AI only) for master-clock generation.
 
 The programmer should ensure the define in :ref:`opt_spdif_rx_ref_defines` is set appropriately.
 

lib_xua/doc/rst/sw_clocking.rst

@@ -15,17 +15,18 @@ the xCORE.
 
 Using an external PLL/Clock Multiplier allows an Asynchronous mode design to lock to an external
 clock source from a digital stream (e.g. S/PDIF or ADAT input).  The codebase supports the Cirrus
-Logic CS2100 device for this purpose. Other devices may be supported via code modification.
+Logic CS2100 device or use of lib_sw_pll (xCORE-AI only) for this purpose. Other devices may be 
+supported via code modification.
 
-.. note::
-   
-    It is expected that in a future release  the secondary PLL in xCORE.ai devices, coupled with
-    associated software changes, will be capable of replacing the CS2100 part for most designs.
+The Clock Recovery core (Clock Gen) is responsible for either generating the reference frequency 
+to the CS2100 device or driving lib_sw_pll from time measurements based on the local master clock
+and the time of received samples. Clock Gen (via CS2100 or lib_sw_pll) generates the master clock 
+used over the whole design. This core also serves as a smaller buffer between ADAT and S/PDIF 
+receiving cores and the Audio Hub core.
 
-The Clock Recovery core (Clock Gen) is responsible for generating the reference frequency 
-to the CS2100 device. This, in turn, generates the master clock used over the whole design.
-This core also serves as a smaller buffer between ADAT and S/PDIF receiving cores and the Audio Hub
-core.
+When using lib_sw_pll (xCORE-AI only) an further core is instantiated which performs the sigma-delta
+modulation of the xCORE PLL to ensure the lowest jitter over the audio band. See lib_sw_pll
+documentation for further details.
 
 When running in *Internal Clock* mode this core simply generates this clock using a local
 timer, based on the XMOS reference clock.