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make use of # guards and nullable consistent

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Ed
2024-01-15 17:28:38 +00:00
parent ca16467158
commit af9a6b18b2
4 changed files with 48 additions and 52 deletions
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20
lib_xua/api/xua_clocking.h
View File

@@ -39,22 +39,12 @@ void clockGen( streaming chanend ?c_spdif_rx,
chanend c_audio,
chanend c_clk_ctl,
chanend c_clk_int,
chanend c_mclk_change,
port ?p_for_mclk_count_aud,
chanend ?c_sw_pll);
#if (XUA_USE_APP_PLL)
interface SoftPll_if
{
void init(int mclk_hz);
};
#if (XUA_SYNCMODE == XUA_SYNCMODE_ASYNC)
[[distributable]]
chanend c_mclk_change
#if USE_SW_PLL
, port p_for_mclk_count_aud
, chanend c_sw_pll
#endif
void XUA_SoftPll(tileref tile, server interface SoftPll_if i_softPll, chanend c_update);
);
#endif
#endif

33
lib_xua/src/core/clocking/clockgen.xc
View File

@@ -222,9 +222,12 @@ void clockGen ( streaming chanend ?c_spdif_rx,
chanend c_dig_rx,
chanend c_clk_ctl,
chanend c_clk_int,
chanend c_mclk_change,
port ?p_for_mclk_count_aud,
chanend ?c_sw_pll)
chanend c_mclk_change
#if USE_SW_PLL
, port p_for_mclk_count_aud
, chanend c_sw_pll
#endif
)
{
timer t_local;
unsigned timeNextEdge, timeLastEdge, timeNextClockDetection;
@@ -243,13 +246,14 @@ void clockGen ( streaming chanend ?c_spdif_rx,
timer t_external;
unsigned selected_mclk_rate = MCLK_48; // Assume 24.576MHz initial clock
unsigned selected_sample_rate = 0;
#if USE_SW_PLL
unsigned mclks_per_sample = 0;
unsigned short mclk_time_stamp = 0;
/* Get MCLK count */
if(!isnull(p_for_mclk_count_aud))
{
asm volatile(" getts %0, res[%1]" : "=r" (mclk_time_stamp) : "r" (p_for_mclk_count_aud));
}
asm volatile(" getts %0, res[%1]" : "=r" (mclk_time_stamp) : "r" (p_for_mclk_count_aud));
#endif
#endif
#if (XUA_SPDIF_RX_EN)
@@ -548,11 +552,10 @@ void clockGen ( streaming chanend ?c_spdif_rx,
/* Receive sample from S/PDIF RX thread (streaming chan) */
case c_spdif_rx :> spdifRxData:
#if USE_SW_PLL
/* Record time of sample */
if(!isnull(p_for_mclk_count_aud))
{
asm volatile(" getts %0, res[%1]" : "=r" (mclk_time_stamp) : "r" (p_for_mclk_count_aud));
}
asm volatile(" getts %0, res[%1]" : "=r" (mclk_time_stamp) : "r" (p_for_mclk_count_aud));
#endif
t_local :> spdifRxTime;
/* Check parity and ignore if bad */
@@ -642,11 +645,11 @@ void clockGen ( streaming chanend ?c_spdif_rx,
#if (XUA_ADAT_RX_EN)
/* receive sample from ADAT rx thread (streaming channel with CT_END) */
case inuint_byref(c_adat_rx, tmp):
#if USE_SW_PLL
/* record time of sample */
if(!isnull(p_for_mclk_count_aud))
{
asm volatile(" getts %0, res[%1]" : "=r" (mclk_time_stamp) : "r" (p_for_mclk_count_aud));
}
asm volatile(" getts %0, res[%1]" : "=r" (mclk_time_stamp) : "r" (p_for_mclk_count_aud));
#endif
t_local :> adatReceivedTime;
/* Sync is: 1 | (user_byte << 4) */

26
lib_xua/src/core/clocking/sw_pll_wrapper.xc
View File

@@ -10,7 +10,7 @@
#if USE_SW_PLL
{unsigned, unsigned} InitSWPLL(sw_pll_state_t &sw_pll, unsigned mClk)
{unsigned, unsigned} init_sw_pll(sw_pll_state_t &sw_pll, unsigned mClk)
{
/* Autogenerated SDM App PLL setup by dco_model.py using 22.5792_1M profile */
/* Input freq: 24000000
@@ -74,7 +74,7 @@
void do_sw_pll_phase_frequency_detector_dig_rx( unsigned short mclk_time_stamp,
unsigned mclks_per_sample,
chanend c_sigma_delta,
chanend c_sw_pll,
int receivedSamples,
int &reset_sw_pll_pfd)
{
@@ -106,7 +106,7 @@ void do_sw_pll_phase_frequency_detector_dig_rx( unsigned short mclk_time_stamp,
}
/* send PFD output to the sigma delta thread */
outuint(c_sigma_delta, (int) f_error);
outuint(c_sw_pll, (int) f_error);
last_mclk_time_stamp = mclk_time_stamp;
control_loop_counter = 0;
@@ -114,22 +114,22 @@ void do_sw_pll_phase_frequency_detector_dig_rx( unsigned short mclk_time_stamp,
}
}
void sw_pll_task(chanend c_sigma_delta){
void sw_pll_task(chanend c_sw_pll){
/* Zero is an invalid number and the SDM will not write the frac reg until
the first control value has been received. This avoids issues with
channel lockup if two tasks (eg. init and SDM) try to write at the same time. */
while(1)
{
unsigned selected_mclk_rate = inuint(c_sigma_delta);
unsigned selected_mclk_rate = inuint(c_sw_pll);
int f_error = 0;
int dco_setting = 0; /* gets set at InitSWPLL */
unsigned sdm_interval = 0; /* gets set at InitSWPLL */
int dco_setting = 0; /* gets set at init_sw_pll */
unsigned sdm_interval = 0; /* gets set at init_sw_pll */
sw_pll_state_t sw_pll;
/* initialse the SDM and gather SDM initial settings */
{sdm_interval, dco_setting} = InitSWPLL(sw_pll, selected_mclk_rate);
{sdm_interval, dco_setting} = init_sw_pll(sw_pll, selected_mclk_rate);
tileref_t this_tile = get_local_tile_id();
@@ -138,7 +138,7 @@ void sw_pll_task(chanend c_sigma_delta){
tmr :> time_trigger;
int running = 1;
outuint(c_sigma_delta, 0); /* Signal back via clockgen to audio to start I2S */
outuint(c_sw_pll, 0); /* Signal back via clockgen to audio to start I2S */
unsigned rx_word = 0;
while(running)
@@ -146,7 +146,7 @@ void sw_pll_task(chanend c_sigma_delta){
/* Poll for new SDM control value */
select
{
case inuint_byref(c_sigma_delta, rx_word):
case inuint_byref(c_sw_pll, rx_word):
if(rx_word == DISABLE_SDM)
{
f_error = 0;
@@ -186,10 +186,10 @@ void sw_pll_task(chanend c_sigma_delta){
}
void restart_sigma_delta(chanend c_sigma_delta, unsigned selected_mclk_rate)
void restart_sigma_delta(chanend c_sw_pll, unsigned selected_mclk_rate)
{
outuint(c_sigma_delta, DISABLE_SDM); /* Resets SDM */
outuint(c_sigma_delta, selected_mclk_rate);
outuint(c_sw_pll, DISABLE_SDM); /* Resets SDM */
outuint(c_sw_pll, selected_mclk_rate);
}
#endif /* USE_SW_PLL */

21
lib_xua/src/core/main.xc
View File

@@ -329,13 +329,13 @@ void usb_audio_io(chanend ?c_aud_in,
chan c_dig_rx;
chan c_mclk_change; /* Notification of new mclk freq to clockgen */
#if USE_SW_PLL
/* Connect p_for_mclk_count_aud to clk_audio_mclk so we can count mclks/timestamp in digital rx*/
if(!isnull(p_for_mclk_count_aud))
{
unsigned x = 0;
asm("ldw %0, dp[clk_audio_mclk]":"=r"(x));
asm("setclk res[%0], %1"::"r"(p_for_mclk_count_aud), "r"(x));
}
unsigned x = 0;
asm("ldw %0, dp[clk_audio_mclk]":"=r"(x));
asm("setclk res[%0], %1"::"r"(p_for_mclk_count_aud), "r"(x));
#endif /* USE_SW_PLL */
#endif /* (XUA_SPDIF_RX_EN || XUA_ADAT_RX_EN) */
#if (XUA_NUM_PDM_MICS > 0) && (PDM_TILE == AUDIO_IO_TILE)
@@ -408,9 +408,12 @@ void usb_audio_io(chanend ?c_aud_in,
c_dig_rx,
c_clk_ctl,
c_clk_int,
c_mclk_change,
p_for_mclk_count_aud,
c_sw_pll);
c_mclk_change
#if USE_SW_PLL
, p_for_mclk_count_aud
, c_sw_pll
#endif
);
}
#endif