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Changelog update

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This commit is contained in:
xross
2022-09-28 11:27:12 +01:00
parent e1d0974912
commit b7a90a3235
3 changed files with 13 additions and 8 deletions
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3
CHANGELOG.rst
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@@ -7,6 +7,9 @@ UNRELEASED
* CHANGED: Define ADAT_RX renamed to XUA_ADAT_RX_EN
* CHANGED: Define ADAT_TX renamed to XUA_ADAT_TX_EN
* CHANGED: Define SPDIF_RX renamed to XUA_SPDIF_RX_EN
* CHANGED: Drive strength of I2S clock lines upped to 8mA on xCORE.ai
* CHANGED: ADC datalines sampled on falling edge of clock in TDM mode
* CHANGED: Improved startup behaviour of TDM clocks
* FIXED: Intermittent underflow at MAX_FREQ on input stream start due to
insufficient packet buffering

6
lib_xua/src/core/audiohub/audiohub_initport.xc
View File

@@ -52,10 +52,10 @@ void InitPorts_master(unsigned divide, buffered _XUA_CLK_DIR port:32 p_lrclk, bu
}
#endif
if(XUA_PCM_FORMAT == XUA_PCM_FORMAT_TDM)
p_lrclk @ tmp <: 0x80000000;
if(XUA_PCM_FORMAT == XUA_PCM_FORMAT_TDM)
p_lrclk @ tmp <: 0x80000000;
else
p_lrclk @ tmp <: 0x7FFFFFFF;
p_lrclk @ tmp <: 0x7FFFFFFF;
#if (I2S_CHANS_ADC != 0)
for(int i = 0; i < I2S_WIRES_ADC; i++)

12
lib_xua/src/core/ports/audioports.xc
View File

@@ -78,11 +78,13 @@ void ConfigAudioPorts(
configure_out_port_no_ready(p_lrclk, clk_audio_bclk, 0);
}
if(XUA_PCM_FORMAT == XUA_PCM_FORMAT_TDM)
{
for(int i = 0; i < I2S_WIRES_ADC; i++)
set_port_sample_delay(p_i2s_adc[i]);
}
if(XUA_PCM_FORMAT == XUA_PCM_FORMAT_TDM)
{
for(int i = 0; i < I2S_WIRES_ADC; i++)
{
set_port_sample_delay(p_i2s_adc[i]);
}
}
#elif (CODEC_MASTER)