Fix xcore.ai branding

CHANGELOG.rst

@@ -13,7 +13,7 @@ HEAD
   * RESOLVED:  Repeated old S/PDIF and ADAT samples when entering underflow state
   * CHANGED:   QUAD_SPI_FLASH replaced by XUA_QUAD_SPI_FLASH (default: 1)
   * CHANGED:   UserBufferManagementInit() now takes a sample rate parameter
-  * CHANGED:   xcore-ai targets use sigma-delta software PLL for clock recovery of
+  * CHANGED:   xcore.ai targets use sigma-delta software PLL for clock recovery of
     digital Rx streams by default.
 
   * Changes to dependencies:

lib_xua/doc/rst/arch.rst

@@ -54,7 +54,7 @@ In addition :ref:`usb_audio_optional_components` shows optional components that
  * - Clockgen
    - Drives an external frequency generator (PLL) and manages
      changes between internal clocks and external clocks arising
-     from digital input. On xCORE-AI Clockgen may also work in
+     from digital input. On xcore.ai Clockgen may also work in
      conjunction with lib_sw_pll to produce a local clock from 
      the XCORE which is locked to the incoming digital stream.
  * - MIDI

lib_xua/doc/rst/feat_spdif_rx.rst

@@ -29,7 +29,7 @@ The S/PDIF receiver should be called on the appropriate tile::
 With the steps above an S/PDIF stream can be captured by the xCORE. To be functionally useful the audio
 master clock must be able to synchronise to this external digital stream. Additionally, the host can be 
 notified regarding changes in the validity of this stream, it's frequency etc. To synchronise to external 
-streams the codebase assumes the use of an external Cirrus Logic CS2100 device or lib_sw_pll on xCORE-AI designs.
+streams the codebase assumes the use of an external Cirrus Logic CS2100 device or lib_sw_pll on xcore.ai designs.
 
 The ``ClockGen()`` task from ``lib_xua`` provides the reference signal to the CS2100 device or timing information
 to lib_sw_pll and also handles recording of clock validity etc.

lib_xua/doc/rst/hw.rst

@@ -56,7 +56,7 @@ Three methods of generating an audio master clock are provided on the board:
 
 Selection between these methods is done via writing to bits 6 and 7 of PORT 8D on tile[0]. 
 
-Either the locally generated clock (from the PL611) or the recovered low jitter clock (from the CS2100) may be selected to clock the audio stages; the xCORE-AI, the ADC/DAC and Digital output stages. Selection is controlled via an additional I/O, bit 5 of PORT 8C, see :ref:`hw_316_ctrlport`.
+Either the locally generated clock (from the PL611) or the recovered low jitter clock (from the CS2100) may be selected to clock the audio stages; the xcore.ai, the ADC/DAC and Digital output stages. Selection is controlled via an additional I/O, bit 5 of PORT 8C, see :ref:`hw_316_ctrlport`.
 
 .. _hw_316_ctrlport:
 

lib_xua/doc/rst/opt_spdif_rx.rst

@@ -34,7 +34,7 @@ This must be a 1-bit port, for example::
     <Port Location="XS1_PORT_1A"  Name="PORT_SPDIF_IN"/>
 
 When S/PDIF receive is enabled the codebase expects to either drive a synchronisation signal to an external 
-Cirrus Logic CS2100 device or use lib_swp_pll (xCORE-AI only) for master-clock generation.
+Cirrus Logic CS2100 device or use lib_swp_pll (xcore.ai only) for master-clock generation.
 
 The programmer should ensure the define in :ref:`opt_spdif_rx_ref_defines` is set appropriately.
 

lib_xua/doc/rst/sw_clocking.rst

@@ -15,7 +15,7 @@ the xCORE.
 
 Using an external PLL/Clock Multiplier allows an Asynchronous mode design to lock to an external
 clock source from a digital stream (e.g. S/PDIF or ADAT input).  The codebase supports the Cirrus
-Logic CS2100 device or use of lib_sw_pll (xCORE-AI only) for this purpose. Other devices may be 
+Logic CS2100 device or use of lib_sw_pll (xcore.ai only) for this purpose. Other devices may be 
 supported via code modification.
 
 The Clock Recovery core (Clock Gen) is responsible for either generating the reference frequency 
@@ -24,7 +24,7 @@ and the time of received samples. Clock Gen (via CS2100 or lib_sw_pll) generates
 used over the whole design. This core also serves as a smaller buffer between ADAT and S/PDIF 
 receiving cores and the Audio Hub core.
 
-When using lib_sw_pll (xCORE-AI only) an further core is instantiated which performs the sigma-delta
+When using lib_sw_pll (xcore.ai only) an further core is instantiated which performs the sigma-delta
 modulation of the xCORE PLL to ensure the lowest jitter over the audio band. See lib_sw_pll
 documentation for further details.
 
@@ -35,7 +35,7 @@ When running in an external clock mode (i.e. S/PDIF Clock" or "ADAT Clock" mode)
 received from the S/PDIF and/or ADAT receive core. The external frequency is calculated through 
 counting samples in a given period. Either the reference clock to the CS2100 is then generated based on
 the reception of these samples or the timing information is provided to lib_sw_pll to generate
-the phase-locked clock on-chip (xCORE-AI only).
+the phase-locked clock on-chip (xcore.ai only).
 
 If an external stream becomes invalid, the *Internal Clock* timer event will fire to ensure that 
 valid master clock generation continues regardless of cable unplugs etc. Efforts are made to 

lib_xua/src/core/clocking/sw_pll_wrapper.h

@@ -4,7 +4,7 @@
 #ifndef _SW_PLL_WRAPPPER_H_
 #define _SW_PLL_WRAPPPER_H_
 
-/* By default we use SW_PLL for Digital Rx configs running on XCORE-AI */
+/* By default we use SW_PLL for Digital Rx configs running on xcore.ai */
 /* Note: Not yet implemented for Synchronous mode */
 #ifdef __XS3A__
 #ifndef USE_SW_PLL