Documentation updates (related to AudioHub/I2S)
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Features & Options
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------------------
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The previous sections describes only the basic core set of ``lib_xua`` details on enabling additional features e.g. S/PDIF are discussed in this section.
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If using the "codeless" programming model then the steps in this section are informational only.
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@@ -25,14 +24,10 @@ Ports for the sample and bit clocks are also required::
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.. note::
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All of these ports must be buffered, width 32
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All of these ports must be buffered, width 32. Based on whether the xCORE is bus slave/master the ports must be declared as input/output respectively
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These ports must then be passed to the ``XUA_AudioHub()`` task appropriately.
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.. note::
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Based on whether the xCORE is bus slave/master the ports must be declared as input/output respectively
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I2S functionality also requires two clock-blocks, one for bit and sample clock e.g.::
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/* Clock-block declarations */
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@@ -31,6 +31,7 @@ Older versions of Windows are not guaranteed to operate as expected. Devices are
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Software Overview <sw>
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Using lib_xua <using>
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Features <feat>
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Software Detail <sw_detail>
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Known Issues <issues>
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@@ -1,28 +1,26 @@
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.. _usb_audio_sec_audio:
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Audio Driver
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AudioHub/I2S
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............
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The audio driver receives and transmits samples from/to the decoupler
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or mixer core over an XC channel.
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It then drives several in and out I2S/TDM channels. If
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the firmware is configured with the CODEC as slave, it will also
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drive the word and bit clocks in this core as well. The word
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clocks, bit clocks and data are all derived from the incoming
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master clock (typically the output of the external oscillator or PLL). The audio
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driver is implemented in the file ``audio.xc``.
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The AudioHub task performs many functions. It receives and transmits samples from/to the decoupler or mixer core over an XC channel.
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The audio driver captures and plays audio data over I2S. It also
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forwards on relevant audio data to the S/PDIF transmit core.
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It also drives several in and out I2S/TDM channels to/from a CODEC, DAC, ADC etc - from now on termed "audio hardware".
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The audio core must be connected to a CODEC that supports I2S (other
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modes such as "left justified" can be supported with firmware changes). In
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slave mode, the XMOS device acts as the master generating the Bit
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Clock (BCLK) and Left-Right Clock (LRCLK, also called Word Clock)
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signals. Any CODEC or DAC/ADC combination that supports I2S and can be used.
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If the firmware is configured with the xCORE as I2S master the requred clock lines will also be driven out from this task also.
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:ref:`usb_audio_codec_signals` shows the signals used to communicate audio between
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the XMOS device and the CODEC.
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It also has the task of formwarding on and reciving samples to/from other audio related tasks such as S/PDIF tasks, ADAT tasks etc.
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The AudioHub task must be connected to external audio hardware that supports I2S (other modes such as "left justified" can be supported with firmware changes).
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In master mode, the XMOS device acts as the master generating the I2S "Continous Serial Clock (SCK)" typically called the Bit-Clock (BCLK) and the "Word Select (WS)" line typically called left-right clock (LRCLK) signals. Any CODEC or DAC/ADC combination that supports I2S and can be used.
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The LR-clock, bit-clock and data are all derived from the incoming master clock (typically the output of the external oscillator or PLL)
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- This is not part of the I2S standard but is commonly included for synchronizing the internal operation of the analog/digital converters.
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The AudioHub task is implemented in the file ``xua_audiohub.xc``.
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:ref:`usb_audio_codec_signals` shows the signals used to communicate audio between the XMOS device and the external audio hardware.
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.. _usb_audio_codec_signals:
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@@ -43,16 +41,16 @@ the XMOS device and the CODEC.
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* - MCLK
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- The master clock running the CODEC/DAC/ADC
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The bit clock controls the rate at which data is transmitted to and from the CODEC.
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The bit clock controls the rate at which data is transmitted to and from the external audio hardware.
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In the case where the XMOS device is the master, it divides the MCLK to generate the required signals for both BCLK and LRCLK,
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with BCLK then being used to clock data in (SDIN) and data out (SDOUT) of the CODEC.
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with BCLK then being used to clock data in (SDIN) and data out (SDOUT) of the external audio hardware.
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:ref:`usb_audio_l1_clock_divides` shows some example clock frequencies and divides
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for different sample rates (note that this reflects the single tile L-Series reference board configuration):
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:ref:`usb_audio_example_clock_divides` shows some example clock frequencies and divides for different sample rates:
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.. _usb_audio_l1_clock_divides:
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.. _usb_audio_example_clock_divides:
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.. list-table:: Clock Divides used in single tile L-Series Ref Design
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.. list-table:: Clock Divide examples
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:header-rows: 1
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:widths: 30 25 25 20
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@@ -85,18 +83,16 @@ for different sample rates (note that this reflects the single tile L-Series ref
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- 12.288
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- 2
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The master clock must be supplied by an external source e.g. clock generator,
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fixed oscillators, PLL etc to generate the two frequencies to support
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44.1kHz and 48kHz audio frequencies (e.g. 11.2896/22.5792MHz and 12.288/24.576MHz
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respectively). This master clock input is then provided to the CODEC and
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the XMOS device.
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The master clock must be supplied by an external source e.g. clock generator, fixed oscillators, PLL etc to generate the two frequencies to support
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44.1kHz and 48kHz audio frequencies (e.g. 11.2896/22.5792MHz and 12.288/24.576MHzrespectively). This master clock input is then provided to the
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external audio hardware and the xCORE device.
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Port Configuration (xCORE Master)
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+++++++++++++++++++++++++++++++++
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The default software configuration is CODEC Slave (xCORE master). That is, the XMOS device
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provides the BCLK and LRCLK signals to the CODEC.
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The default software configuration is xCORE is I2S master. That is, the XMOS device
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provides the BCLK and LRCLK signals to the audio hardware
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XS1 ports and XMOS clocks provide many valuable features for
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implementing I2S. This section describes how these are configured
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@@ -4,10 +4,14 @@ Implementation Detail
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This section describes the software architecture of a USB Audio device implemented using `lib_xua`, it's dependancies and other supporting libraries.
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This section will now examine these components in further detail.
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This section will now examine the operation of these components in further detail.
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.. toctree::
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sw_audio
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..
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sw_xud
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sw_ep0
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sw_audio
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@@ -18,5 +22,6 @@ This section will now examine these components in further detail.
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sw_clocking
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sw_midi
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sw_pdm
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sw_resource
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sw_resource
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..
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