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Ed
2024-01-05 14:40:14 +00:00
parent 56d728f349
commit 4962cebc9c
1 changed files with 3 additions and 3 deletions
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6
lib_xua/src/core/clocking/clockgen.xc
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@@ -352,11 +352,11 @@ void SigmaDeltaTask(chanend c_sigma_delta, unsigned sdm_interval){
the first control value has been received. This avoids issues with the first control value has been received. This avoids issues with
channel lockup if two tasks (eg. init and SDM) try to write at the same time. */ channel lockup if two tasks (eg. init and SDM) try to write at the same time. */
/* To be extra safe, spin on sw_pll_ptr until it has been initialised */ /* To be extra safe, spin on sw_pll_ptr until it has been initialised by clockgen */
while(sw_pll_ptr == NULL); while(sw_pll_ptr == NULL);
int f_error = 0; int f_error = 0;
int dco_setting = SW_PLL_SDM_CTRL_MID_24; // TODO Assume 24.576MHz? int dco_setting = SW_PLL_SDM_CTRL_MID_24; // Assume 24.576MHz as initial clock
unsafe unsafe
{ {
sw_pll_init_sigma_delta(&sw_pll_ptr->sdm_state); sw_pll_init_sigma_delta(&sw_pll_ptr->sdm_state);
@@ -578,7 +578,7 @@ void clockGen ( streaming chanend ?c_spdif_rx,
sw_pll_ptr = &sw_pll; sw_pll_ptr = &sw_pll;
} }
unsigned sdm_interval = InitSWPLL(sw_pll, MCLK_48); unsigned sdm_interval = InitSWPLL(sw_pll, MCLK_48); // Assume 24.576MHz initial clock
par par
{ {