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Set DCO to midpoint of SDM restart

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Ed
2024-01-15 10:05:53 +00:00
parent ce987622d9
commit 57debd0558
3 changed files with 11 additions and 10 deletions
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6
lib_xua/src/core/clocking/clockgen.xc
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@@ -535,7 +535,7 @@ void clockGen ( streaming chanend ?c_spdif_rx,
#if ((XUA_SPDIF_RX_EN || XUA_ADAT_RX_EN) && USE_SW_PLL)
case inuint_byref(c_sigma_delta, tmp):
printstr("ACK\n");
/* Send ACK back to audiohub to allow I2S to start */
if(require_ack_to_audio)
{
c_mclk_change <: tmp;
@@ -545,9 +545,9 @@ void clockGen ( streaming chanend ?c_spdif_rx,
#endif
#if (XUA_SPDIF_RX_EN || XUA_ADAT_RX_EN)
/* Receive notification of audio streaming settings change */
case c_mclk_change :> selected_mclk_rate:
c_mclk_change :> selected_sample_rate;
printintln(selected_sample_rate);
#if USE_SW_PLL
mclks_per_sample = selected_mclk_rate / selected_sample_rate;
restart_sigma_delta(c_sigma_delta);
@@ -555,7 +555,7 @@ void clockGen ( streaming chanend ?c_spdif_rx,
/* We will shedule an ACK when sigma delta is up and running */
require_ack_to_audio = 1;
#else
/* Send ACK immediately as we are good to go */
/* Send ACK immediately as we are good to go if not using SW_PLL */
c_mclk_change <: 0;
#endif
break;

5
lib_xua/src/core/clocking/sw_pll_wrapper.h
View File

@@ -57,8 +57,9 @@ void do_sw_pll_phase_frequency_detector_dig_rx( unsigned short mclk_time_stamp,
*
* \param sw_pll Reference to a software pll state struct to be initialised.
* \param mClk The current nominal mClk frequency.
*/
unsigned InitSWPLL(sw_pll_state_t &sw_pll, unsigned mClk);
*
* returns The SDM update interval and the initial DCO setting for nominal frequency */
{unsigned, unsigned} InitSWPLL(sw_pll_state_t &sw_pll, unsigned mClk);
#endif /* USE_SW_PLL */
#endif /* _SW_PLL_WRAPPPER_H_ */

10
lib_xua/src/core/clocking/sw_pll_wrapper.xc
View File

@@ -10,7 +10,7 @@
#if USE_SW_PLL
unsigned InitSWPLL(sw_pll_state_t &sw_pll, unsigned mClk)
{unsigned, unsigned} InitSWPLL(sw_pll_state_t &sw_pll, unsigned mClk)
{
/* Autogenerated SDM App PLL setup by dco_model.py using 22.5792_1M profile */
/* Input freq: 24000000
@@ -69,7 +69,7 @@ unsigned InitSWPLL(sw_pll_state_t &sw_pll, unsigned mClk)
/* Reset SDM too */
sw_pll_init_sigma_delta(&sw_pll.sdm_state);
return (XS1_TIMER_HZ / sw_pll_sdm_rate[clkIndex]);
return {XS1_TIMER_HZ / sw_pll_sdm_rate[clkIndex], sw_pll_sdm_ctrl_mid[clkIndex]};
}
void do_sw_pll_phase_frequency_detector_dig_rx( unsigned short mclk_time_stamp,
@@ -120,14 +120,14 @@ void SigmaDeltaTask(chanend c_sigma_delta, unsigned * unsafe selected_mclk_rate_
channel lockup if two tasks (eg. init and SDM) try to write at the same time. */
int f_error = 0;
int dco_setting = SW_PLL_SDM_CTRL_MID_24; // Assume 24.576MHz as initial clock
unsigned sdm_interval = 0;
int dco_setting = 0; /* gets set at InitSWPLL */
unsigned sdm_interval = 0; /* gets set at InitSWPLL */
sw_pll_state_t sw_pll;
unsafe
{
printf("SigmaDeltaTask: %u\n", *selected_mclk_rate_ptr);
sdm_interval = InitSWPLL(sw_pll, (unsigned)*selected_mclk_rate_ptr);
{sdm_interval, dco_setting} = InitSWPLL(sw_pll, (unsigned)*selected_mclk_rate_ptr);
}
tileref_t this_tile = get_local_tile_id();