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Remove debug prints

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Ed
2024-01-09 13:32:41 +00:00
parent 2fcc9ca2ac
commit 91d23fb1d6
2 changed files with 0 additions and 10 deletions
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6
lib_xua/src/core/clocking/clockgen.xc
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@@ -551,11 +551,9 @@ void clockGen ( streaming chanend ?c_spdif_rx,
c_mclk_change :> selected_sample_rate;
mclks_per_sample = selected_mclk_rate / selected_sample_rate;
#if USE_SW_PLL
printstr("c_mclk_change: "); printuintln(selected_mclk_rate);
disable_sigma_delta(c_sigma_delta); /* Blocks until SDM is idle */
InitSWPLL(sw_pll, selected_mclk_rate);
reset_sw_pll_pfd = 1;
printstr("swpll int'd\n");
c_mclk_change <: 0; /* Acknowledge to hold off starting audio until done */
#endif
break;
@@ -605,14 +603,12 @@ void clockGen ( streaming chanend ?c_spdif_rx,
if(spdifSamps > MAX_SPDIF_SAMPLES-1)
{
spdifOverflow = 1;
printstr("spo+\n"); // DELME
}
/* Check for coming out of under flow */
if(spdifUnderflow && (spdifSamps >= (MAX_SPDIF_SAMPLES >> 1)))
{
spdifUnderflow = 0;
printstr("spu-\n"); // DELME
}
}
break;
@@ -810,7 +806,6 @@ void clockGen ( streaming chanend ?c_spdif_rx,
{
/* We're out of S/PDIF samples, mark underflow condition */
spdifUnderflow = 1;
printstr("spu+\n"); // DELME
spdifLeft = 0;
}
@@ -819,7 +814,6 @@ void clockGen ( streaming chanend ?c_spdif_rx,
if(spdifOverflow && (spdifSamps < (MAX_SPDIF_SAMPLES>>1)))
{
spdifOverflow = 0;
printstr("spo-\n"); // DELME
}
}
#endif

4
lib_xua/src/core/clocking/sw_pll_wrapper.xc
View File

@@ -75,8 +75,6 @@ unsigned InitSWPLL(sw_pll_state_t &sw_pll, unsigned mClk)
/* Reset SDM too */
sw_pll_init_sigma_delta(&sw_pll.sdm_state);
printstr("Init sw_pll: "); printuintln(mClk);
return (XS1_TIMER_HZ / sw_pll_sdm_rate[clkIndex]);
}
@@ -112,8 +110,6 @@ void do_sw_pll_phase_frequency_detector_dig_rx( unsigned short mclk_time_stamp,
f_error = 0; /* Skip first measurement as it will likely be very out */
reset_sw_pll_pfd = 0;
}
printintln(f_error);
/* send PFD output to the sigma delta thread */
outuint(c_sigma_delta, (int) f_error);