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Output functional in simple app. Issue at high volume. Still uses sc_i2c.

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This commit is contained in:
xross
2017-10-12 15:33:58 +01:00
parent d4775f0122
commit 332ec6fbcb
15 changed files with 222 additions and 183 deletions
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3
examples/app_xua_simple/Makefile
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@@ -8,7 +8,8 @@ XCC_FLAGS = -fcomment-asm -Xmapper --map -Xmapper MAPFILE -O3 -report -fsubw
# The USED_MODULES variable lists other module used by the application. These
# modules will extend the SOURCE_DIRS, INCLUDE_DIRS and LIB_DIRS variables.
# Modules are expected to be in the directory above the BASE_DIR directory.
USED_MODULES = lib_i2c lib_mic_array lib_logging lib_xua lib_device_control lib_src lib_dsp lib_spi lib_xud
USED_MODULES = lib_mic_array lib_logging lib_xua lib_device_control lib_xud module_i2c_shared module_i2c_single_port module_locks
#=============================================================================
# The following part of the Makefile includes the common build infrastructure

68
examples/app_xua_simple/src/app_xua_simple.xc
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@@ -1,8 +1,12 @@
/* A very simple example of a USB audio application (and as such is un-verified)
*
/* A very simple *example* of a USB audio application (and as such is un-verified for production)
*
* It uses the main blocks from the lib_xua
*
* - 2 in/ 2 out I2S only
* - No DFU
* - I2S only
*
*/
#include <xs1.h>
@@ -11,26 +15,21 @@
#include "xud_device.h"
#include "xua.h"
/* Ports - note the defines come from the xn file */
/* Port declarations. Note, the defines come from the xn file */
buffered out port:32 p_i2s_dac[] = {PORT_I2S_DAC0}; /* I2S Data-line(s) */
buffered out port:32 p_lrclk = PORT_I2S_LRCLK; /* I2S Bit-clock */
buffered out port:32 p_bclk = PORT_I2S_BCLK; /* I2S L/R-clock */
/* I2S ports - Data-line, bit-clock and L/R clock */
buffered out port:32 p_i2s_dac[] = {PORT_I2S_DAC0};
buffered out port:32 p_lrclk = PORT_I2S_LRCLK;
buffered out port:32 p_bclk = PORT_I2S_BCLK;
port p_mclk_in = PORT_MCLK_IN; /* Audio master clock input */
/* Audio master-clock port */
port p_mclk_in = PORT_MCLK_IN;
in port p_for_mclk_count = PORT_MCLK_COUNT; /* Extra port for counting master clock ticks */
/* Port for counting master clocks */
in port p_for_mclk_count = PORT_MCLK_COUNT;
/* Clock-blocks for master-clock and bit-clock */
clock clk_audio_bclk = on tile[0]: XS1_CLKBLK_4;
clock clk_audio_mclk = on tile[0]: XS1_CLKBLK_5;
/* Clock-block declarations */
clock clk_audio_bclk = on tile[0]: XS1_CLKBLK_4; /* Bit clock */
clock clk_audio_mclk = on tile[0]: XS1_CLKBLK_5; /* Master clock */
/* Endpoint type tables - informs XUD what the transfer types for each Endpoint in use and also
* if the endpoint wishes to be informed of USB bus resets
*/
* if the endpoint wishes to be informed of USB bus resets */
XUD_EpType epTypeTableOut[] = {XUD_EPTYPE_CTL | XUD_STATUS_ENABLE, XUD_EPTYPE_ISO};
XUD_EpType epTypeTableIn[] = {XUD_EPTYPE_CTL | XUD_STATUS_ENABLE, XUD_EPTYPE_ISO};
@@ -40,13 +39,18 @@ int main()
chan c_ep_out[2];
chan c_ep_in[2];
/* TODO handle this */
chan c_aud_ctl;
/* Channel for communicating SOF notifications from XUD to the Buffering cores */
chan c_sof;
/* Channel for audio data between buffering cores and audio IO core */
chan c_aud;
/* Channel for communcating control messages from EP0 to the rest of the device (via the buffering cores */
chan c_aud_ctl;
/* TODO handle this */
interface audManage_if i_audMan;
par
{
@@ -61,31 +65,13 @@ int main()
/* Note, since we are not using many features we pass in null for quite a few params.. */
on tile[1]: XUA_Endpoint0(c_ep_out[0], c_ep_in[0], c_aud_ctl, null, null, null, null);
/* Buffering cores - handles audio data to/from EP's and gives/gets data from the audio I/O core */
/* Buffering cores - handles audio data to/from EP's and gives/gets data to/from the audio I/O core */
/* Note, this spawns two cores */
on tile[1]: XUA_Buffer(c_ep_out[1], c_ep_in[1], c_sof, c_aud_ctl, p_for_mclk_count, c_aud);
#if 0
/* Audio I/o core i.e. I2S */
on tile[1]: audio(AUDIO_CHANNEL,
#if defined(SPDIF_TX) && (SPDIF_TX_TILE != AUDIO_IO_TILE)
c_spdif_tx,
#endif
#if defined(SPDIF_RX) || defined(ADAT_RX)
c_dig_rx,
#endif
c_aud_cfg, c_adc
#if (XUD_TILE != 0) && (AUDIO_IO_TILE == 0)
, dfuInterface
#endif
#if (NUM_PDM_MICS > 0)
, c_pdm_pcm
#endif
, i_audMan
);
#endif
}
/* IOHub core does most of the audio IO i.e. I2S (also serves as a hub for all audio) */
on tile[0]: XUA_AudioHub(c_aud, i_audMan);
}
return 0;
}

31
examples/app_xua_simple/src/cs4384.h Normal file
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@@ -0,0 +1,31 @@
#ifndef CS4384_H_
#define CS4384_H_
//Address on I2C bus
#define CS4384_I2C_ADDR (0x18)
//Register Addresess
#define CS4384_CHIP_REV 0x01
#define CS4384_MODE_CTRL 0x02
#define CS4384_PCM_CTRL 0x03
#define CS4384_DSD_CTRL 0x04
#define CS4384_FLT_CTRL 0x05
#define CS4384_INV_CTRL 0x06
#define CS4384_GRP_CTRL 0x07
#define CS4384_RMP_MUTE 0x08
#define CS4384_MUTE_CTRL 0x09
#define CS4384_MIX_PR1 0x0a
#define CS4384_VOL_A1 0x0b
#define CS4384_VOL_B1 0x0c
#define CS4384_MIX_PR2 0x0d
#define CS4384_VOL_A2 0x0e
#define CS4384_VOL_B2 0x0f
#define CS4384_MIX_PR3 0x10
#define CS4384_VOL_A3 0x11
#define CS4384_VOL_B3 0x12
#define CS4384_MIX_PR4 0x13
#define CS4384_VOL_A4 0x14
#define CS4384_VOL_B4 0x15
#define CS4384_CM_MODE 0x16
#endif /* CS4384_H_ */

17
examples/app_xua_simple/src/cs5368.h Normal file
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@@ -0,0 +1,17 @@
#ifndef _CS5368_H_
#define _CS5368_H_
//Address on I2C bus
#define CS5368_I2C_ADDR (0x4C)
//Register Addresess
#define CS5368_CHIP_REV 0x00
#define CS5368_GCTL_MDE 0x01
#define CS5368_OVFL_ST 0x02
#define CS5368_OVFL_MSK 0x03
#define CS5368_HPF_CTRL 0x04
#define CS5368_PWR_DN 0x06
#define CS5368_MUTE_CTRL 0x08
#define CS5368_SDO_EN 0x0a
#endif /* _CS5368_H_ */

4
examples/app_xua_simple/src/customdefines.h
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@@ -21,8 +21,8 @@
#define SPDIF_TX_INDEX 0
#define VENDOR_STR "XMOS"
#define VENDOR_ID 0x20B1
#define PRODUCT_STR_A2 "XUA Simple"
#define PRODUCT_STR_A1 "XUA Simple"
#define PRODUCT_STR_A2 "XUA Example"
#define PRODUCT_STR_A1 "XUA Example"
#define PID_AUDIO_1 1
#define PID_AUDIO_2 2
#define AUDIO_CLASS 2

50
examples/app_xua_simple/src/gpio_access.c
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@@ -1,50 +0,0 @@
#include "gpio_access.h"
//#include "swlock.h"
#include <xs1.h>
//swlock_t gpo_swlock = SWLOCK_INITIAL_VALUE;
void p_gpio_lock()
{
//swlock_acquire(&gpo_swlock);
}
void p_gpio_unlock()
{
//swlock_release(&gpo_swlock);
}
unsigned p_gpio_peek()
{
unsigned portId, x;
// Wrapped in lock to ensure it's safe from multiple logical cores
// swlock_acquire(&gpo_swlock);
asm("ldw %0, dp[p_gpio]":"=r"(portId));
asm volatile("peek %0, res[%1]":"=r"(x):"r"(portId));
return x;
}
void p_gpio_out(unsigned x)
{
unsigned portId;
asm("ldw %0, dp[p_gpio]":"=r"(portId));
asm volatile("out res[%0], %1"::"r"(portId),"r"(x));
// Wrapped in lock to ensure it's safe from multiple logical cores
//swlock_release(&gpo_swlock);
}
void set_gpio(unsigned bit, unsigned value)
{
unsigned port_shadow;
port_shadow = p_gpio_peek(); // Read port pin value
if (value == 0) port_shadow &= ~bit; // If writing a 0, generate mask and AND with current val
else port_shadow |= bit; // Else use mask and OR to set bit
p_gpio_out(port_shadow); // Write back to port. Will make port an output if not already
}

51
examples/app_xua_simple/src/gpio_access.h
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@@ -1,51 +0,0 @@
#ifndef _GPIO_ACCESS_H_
#define _GPIO_ACCESS_H_
#include "customdefines.h"
#if XCORE_200_MC_AUDIO_HW_VERSION == 2
/* General output port bit definitions */
#define P_GPIO_DSD_MODE (1 << 0) /* DSD mode select 0 = 8i/8o I2S, 1 = 8o DSD*/
#define P_GPIO_DAC_RST_N (1 << 1)
#define P_GPIO_USB_SEL0 (1 << 2)
#define P_GPIO_USB_SEL1 (1 << 3)
#define P_GPIO_VBUS_EN (1 << 4)
#define P_GPIO_PLL_SEL (1 << 5) /* 1 = CS2100, 0 = Phaselink clock source */
#define P_GPIO_ADC_RST_N (1 << 6)
#define P_GPIO_MCLK_FSEL (1 << 7) /* Select frequency on Phaselink clock. 0 = 24.576MHz for 48k, 1 = 22.5792MHz for 44.1k.*/
#else
/* General output port bit definitions */
#define P_GPIO_DSD_MODE (1 << 0) /* DSD mode select 0 = 8i/8o I2S, 1 = 8o DSD*/
#define P_GPIO_DAC_RST_N (1 << 1)
#define P_GPIO_ADC_RST_N (1 << 2)
#define P_GPIO_USB_SEL0 (1 << 3)
#define P_GPIO_USB_SEL1 (1 << 4)
#define P_GPIO_VBUS_EN (1 << 5)
#define P_GPIO_MCLK_FSEL (1 << 6) /* Select frequency on Phaselink clock. 0 = 24.576MHz for 48k, 1 = 22.5792MHz for 44.1k.*/
#define P_GPIO_PLL_SEL (1 << 7) /* 1 = CS2100, 0 = Phaselink clock source */
#endif
/*LED array defines*/
#define LED_ALL_ON 0xf00f
#define LED_SQUARE_BIG 0x9009
#define LED_SQUARE_SML 0x6006
#define LED_ROW_1 0xf001
#define LED_ROW_2 0xf003
#define LED_ROW_3 0xf007
#define ALL_OFF 0x0000
// LED array masks
#define LED_MASK_COL_OFF 0x7fff
#define LED_MASK_DISABLE 0xffff
void set_gpio(unsigned bit, unsigned value);
void p_gpio_lock();
void p_gpio_unlock();
unsigned p_gpio_peek();
void p_gpio_out(unsigned x);
#endif

127
examples/app_xua_simple/src/hwsupport.xc
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@@ -1,20 +1,135 @@
// Copyright (c) 2016, XMOS Ltd, All rights reserved
#include <platform.h>
#include <timer.h>
#include "audiohw.h"
#include "customdefines.h"
#include "gpio_access.h"
#include "i2c_shared.h"
#include "cs5368.h"
#include "cs4384.h"
on tile [0] : struct r_i2c r_i2c = {XS1_PORT_4A};
void AudioHwConfig(unsigned samFreq, unsigned mClk, chanend ?c_codec, unsigned dsdMode,
/* General output port bit definitions */
#define P_GPIO_DSD_MODE (1 << 0) /* DSD mode select 0 = 8i/8o I2S, 1 = 8o DSD*/
#define P_GPIO_DAC_RST_N (1 << 1)
#define P_GPIO_USB_SEL0 (1 << 2)
#define P_GPIO_USB_SEL1 (1 << 3)
#define P_GPIO_VBUS_EN (1 << 4)
#define P_GPIO_PLL_SEL (1 << 5) /* 1 = CS2100, 0 = Phaselink clock source */
#define P_GPIO_ADC_RST_N (1 << 6)
#define P_GPIO_MCLK_FSEL (1 << 7) /* Select frequency on Phaselink clock. 0 = 24.576MHz for 48k, 1 = 22.5792MHz for 44.1k.*/
#define DAC_REGWRITE(reg, val) {data[0] = val; i2c_shared_master_write_reg(r_i2c, CS4384_I2C_ADDR, reg, data, 1);}
#define DAC_REGREAD(reg, val) {i2c_shared_master_read_reg(r_i2c, CS4384_I2C_ADDR, reg, val, 1);}
#define ADC_REGWRITE(reg, val) {data[0] = val; i2c_shared_master_write_reg(r_i2c, CS5368_I2C_ADDR, reg, data, 1);}
out port p_gpio = on tile[0]:XS1_PORT_8C;
void AudioHwConfig(unsigned samFreq, unsigned mClk, unsigned dsdMode,
unsigned sampRes_DAC, unsigned sampRes_ADC)
{
// nothing
unsigned char data[1] = {0};
unsigned char gpioVal = 0;
/* Set master clock select appropriately and put ADC and DAC into reset */
if (mClk == MCLK_441)
{
gpioVal = P_GPIO_USB_SEL0 | P_GPIO_USB_SEL1;
}
else
{
gpioVal = P_GPIO_USB_SEL0 | P_GPIO_USB_SEL1 | P_GPIO_MCLK_FSEL;
}
p_gpio <: gpioVal;
/* Allow MCLK to settle */
delay_microseconds(20000);
/* Take ADC out of reset */
gpioVal |= P_GPIO_ADC_RST_N;
p_gpio <: gpioVal;
/* Configure ADC for I2S slave mode via I2C */
unsigned dif = 0, mode = 0;
dif = 0x01; /* I2S */
mode = 0x03; /* Slave mode all speeds */
/* Reg 0x01: (GCTL) Global Mode Control Register
* Bit[7]: CP-EN: Manages control-port mode
* Bit[6]: CLKMODE: Setting puts part in 384x mode
* Bit[5:4]: MDIV[1:0]: Set to 01 for /2
* Bit[3:2]: DIF[1:0]: Data Format: 0x01 for I2S, 0x02 for TDM
* Bit[1:0]: MODE[1:0]: Mode: 0x11 for slave mode
*/
ADC_REGWRITE(CS5368_GCTL_MDE, 0b10010000 | (dif << 2) | mode);
/* Reg 0x06: (PDN) Power Down Register */
/* Bit[7:6]: Reserved
* Bit[5]: PDN-BG: When set, this bit powers-own the bandgap reference
* Bit[4]: PDM-OSC: Controls power to internal oscillator core
* Bit[3:0]: PDN: When any bit is set all clocks going to that channel pair are turned off
*/
ADC_REGWRITE(CS5368_PWR_DN, 0b00000000);
/* Configure DAC with PCM values. Note 2 writes to mode control to enable/disable freeze/power down */
/* Take DAC out of reset */
gpioVal |= P_GPIO_DAC_RST_N;
p_gpio <: gpioVal;
delay_microseconds(500);
/* Mode Control 1 (Address: 0x02) */
/* bit[7] : Control Port Enable (CPEN) : Set to 1 for enable
* bit[6] : Freeze controls (FREEZE) : Set to 1 for freeze
* bit[5] : PCM/DSD Selection (DSD/PCM) : Set to 0 for PCM
* bit[4:1] : DAC Pair Disable (DACx_DIS) : All Dac Pairs enabled
* bit[0] : Power Down (PDN) : Powered down
*/
DAC_REGWRITE(CS4384_MODE_CTRL, 0b11000001);
/* PCM Control (Address: 0x03) */
/* bit[7:4] : Digital Interface Format (DIF) : 0b0001 for I2S up to 24bit
* bit[3:2] : Reserved
* bit[1:0] : Functional Mode (FM) : 0x00 - single-speed mode (4-50kHz)
* : 0x01 - double-speed mode (50-100kHz)
* : 0x10 - quad-speed mode (100-200kHz)
* : 0x11 - auto-speed detect (32 to 200kHz)
* (note, some Mclk/SR ratios not supported in auto)
*
*/
unsigned char regVal = 0;
if(samFreq < 50000)
regVal = 0b00010100;
else if(samFreq < 100000)
regVal = 0b00010101;
else //if(samFreq < 200000)
regVal = 0b00010110;
DAC_REGWRITE(CS4384_PCM_CTRL, regVal);
/* Mode Control 1 (Address: 0x02) */
/* bit[7] : Control Port Enable (CPEN) : Set to 1 for enable
* bit[6] : Freeze controls (FREEZE) : Set to 0 for freeze
* bit[5] : PCM/DSD Selection (DSD/PCM) : Set to 0 for PCM
* bit[4:1] : DAC Pair Disable (DACx_DIS) : All Dac Pairs enabled
* bit[0] : Power Down (PDN) : Not powered down
*/
DAC_REGWRITE(CS4384_MODE_CTRL, 0b10000000);
return;
}
void AudioHwInit(chanend ?c_codec)
void AudioHwInit()
{
set_gpio(P_GPIO_USB_SEL0, 1);
set_gpio(P_GPIO_USB_SEL1, 1);
/* Set USB Mux to micro-b */
/* ADC and DAC in reset */
p_gpio <: P_GPIO_USB_SEL0 | P_GPIO_USB_SEL1;
/* Init the i2c module */
i2c_shared_master_init(r_i2c);
}

2
lib_xua/api/xua.h
View File

@@ -2,7 +2,7 @@
#ifndef __XUA_H__
#define __XUA_H__
#include "xua_audio.h"
#include "xua_audiohub.h"
#include "xua_endpoint0.h"

20
lib_xua/api/xua_audiohub.h
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@@ -1,5 +1,5 @@
#ifndef __audio_h__
#define __audio_h__
#ifndef __XUA_AUDIOHUB_H__
#define __XUA_AUDIOHUB_H__
#if __XC__
@@ -31,15 +31,14 @@ typedef interface audManage_if
* \param c_config An optional channel that will be passed on to the
* CODEC configuration functions.
*/
void XUA_AudioHub(chanend ?c_in,
void XUA_AudioHub(chanend ?c_in
#if defined(SPDIF_TX) && (SPDIF_TX_TILE != AUDIO_IO_TILE)
chanend c_spdif_tx,
#endif
#if(defined(SPDIF_RX) || defined(ADAT_RX))
chanend c_dig,
#endif
chanend ?c_config, chanend ?c_adc
#if (XUD_TILE != 0) && (AUDIO_IO_TILE == 0)
#if (XUD_TILE != 0) && (AUDIO_IO_TILE == 0) && (XUA_DFU_EN == 1)
, server interface i_dfu ?dfuInterface
#endif
#if (NUM_PDM_MICS > 0)
@@ -50,6 +49,15 @@ void XUA_AudioHub(chanend ?c_in,
void SpdifTxWrapper(chanend c_spdif_tx);
/* These functions must be implemented for the CODEC/ADC/DAC arrangement of a specific design */
/* Any required clocking and CODEC initialisation - run once at start up */
void AudioHwInit();
/* Configure audio hardware (clocking, CODECs etc) for a specific mClk/Sample frquency - run on every sample frequency change */
void AudioHwConfig(unsigned samFreq, unsigned mClk, unsigned dsdMode,
unsigned sampRes_DAC, unsigned sampRes_ADC);
#endif // __XC__
#endif // __audio_h__
#endif // __XUA_AUDIOHUB_H__

0
lib_xua/src/usb_audio/audio_io/userbuffermanagement.c → lib_xua/src/usb_audio/audiohub/userbuffermanagement.c
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2
lib_xua/src/usb_audio/audio_io/userbuffermanagement.h → lib_xua/src/usb_audio/audiohub/userbuffermanagement.h
View File

@@ -1,7 +1,7 @@
#ifndef _USERBUFFERMANAGEMENT_H_
#define _USERBUFFERMANAGEMENT_H_
#include "xua_audio.h"
#include "xua_audiohub.h"
#include <xccompat.h>
void UserBufferManagementInit(CLIENT_INTERFACE(audManage_if, i_audMan));

11
lib_xua/src/usb_audio/audio_io/audio_io.xc → lib_xua/src/usb_audio/audiohub/xua_audiohub.xc
View File

@@ -15,9 +15,9 @@
#include <string.h>
#include "devicedefines.h"
#include "xua_audiohub.h"
#include "userbuffermanagement.h"
#include "xua_audio.h"
#include "audioports.h"
#include "audiohw.h"
#include "mic_array_conf.h"
@@ -1107,15 +1107,14 @@ static void dummy_deliver(chanend ?c_out, unsigned &command)
}
}
void XUA_AudioHub(chanend ?c_mix_out,
void XUA_AudioHub(chanend ?c_mix_out
#if defined(SPDIF_TX) && (SPDIF_TX_TILE != AUDIO_IO_TILE)
chanend c_spdif_out,
#endif
#if (defined(ADAT_RX) || defined(SPDIF_RX))
chanend c_dig_rx,
#endif
chanend ?c_config, chanend ?c
#if (XUD_TILE != 0) && (AUDIO_IO_TILE == 0)
#if (XUD_TILE != 0) && (AUDIO_IO_TILE == 0) && (XUA_DFU_EN == 1)
, server interface i_dfu ?dfuInterface
#endif
#if (NUM_PDM_MICS > 0)
@@ -1169,7 +1168,7 @@ chanend ?c_config, chanend ?c
#endif
/* Perform required CODEC/ADC/DAC initialisation */
AudioHwInit(c_config);
AudioHwInit();
while(1)
{
@@ -1281,7 +1280,7 @@ chanend ?c_config, chanend ?c
}
#endif
/* Configure Clocking/CODEC/DAC/ADC for SampleFreq/MClk */
AudioHwConfig(curFreq, mClk, c_config, dsdMode, curSamRes_DAC, curSamRes_ADC);
AudioHwConfig(curFreq, mClk, dsdMode, curSamRes_DAC, curSamRes_ADC);
}
if(!firstRun)

9
lib_xua/src/usb_audio/audiohw.h
View File

@@ -1,13 +1,4 @@
#ifndef _CODEC_H_
#define _CODEC_H_
/* These functions must be implemented for the CODEC/ADC/DAC arrangement of a specific design */
/* Any required clocking and CODEC initialisation - run once at start up */
void AudioHwInit(chanend ?c_codec);
/* Configure audio hardware (clocking, CODECs etc) for a specific mClk/Sample frquency - run on every sample frequency change */
void AudioHwConfig(unsigned samFreq, unsigned mClk, chanend ?c_codec, unsigned dsdMode,
unsigned sampRes_DAC, unsigned sampRes_ADC);
#endif

10
lib_xua/src/usb_audio/main.xc
View File

@@ -419,7 +419,6 @@ void usb_audio_io(chanend ?c_aud_in, chanend ?c_adc,
#ifdef MIXER
chanend c_mix_ctl,
#endif
chanend ?c_aud_cfg,
streaming chanend ?c_spdif_rx,
chanend ?c_adat_rx,
chanend ?c_clk_ctl,
@@ -467,7 +466,6 @@ void usb_audio_io(chanend ?c_aud_in, chanend ?c_adc,
#if defined(SPDIF_RX) || defined(ADAT_RX)
c_dig_rx,
#endif
c_aud_cfg, c_adc
#if (XUD_TILE != 0) && (AUDIO_IO_TILE == 0)
, dfuInterface
#endif
@@ -528,12 +526,6 @@ int main()
chan c_mix_ctl;
#endif
#ifdef AUDIO_CFG_CHAN
chan c_aud_cfg;
#else
#define c_aud_cfg null
#endif
#ifdef SPDIF_RX
streaming chan c_spdif_rx;
#else
@@ -618,7 +610,7 @@ int main()
#ifdef MIXER
, c_mix_ctl
#endif
,c_aud_cfg, c_spdif_rx, c_adat_rx, c_clk_ctl, c_clk_int
, c_spdif_rx, c_adat_rx, c_clk_ctl, c_clk_int
#if (XUD_TILE != 0) && (AUDIO_IO_TILE == 0)
, dfuInterface
#endif