forked from PAWPAW-Mirror/lib_xua
Added DoSampleTransfer() function and updated comments
This commit is contained in:
Ross Owen
@@ -150,284 +150,13 @@ static inline void doI2SClocks(unsigned divide)
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}
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#endif
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/* I2S delivery thread */
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#pragma unsafe arrays
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unsigned static deliver(chanend c_out, chanend ?c_spd_out, unsigned divide, unsigned curSamFreq,
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#if(defined(SPDIF_RX) || defined(ADAT_RX))
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chanend c_dig_rx,
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#endif
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chanend ?c_adc)
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static inline unsigned DoSampleTransfer(chanend c_out, unsigned samplesOut[], unsigned samplesIn[], unsigned underflowWord)
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{
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#if (I2S_CHANS_ADC != 0) || defined(SPDIF)
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unsigned sample;
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#endif
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unsigned underflow = 0;
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#if NUM_USB_CHAN_OUT > 0
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unsigned samplesOut[NUM_USB_CHAN_OUT];
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#endif
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#if NUM_USB_CHAN_IN > 0
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unsigned samplesIn[NUM_USB_CHAN_IN];
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unsigned samplesInPrev[NUM_USB_CHAN_IN];
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#endif
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unsigned tmp;
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#if (I2S_CHANS_ADC != 0)
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unsigned index;
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#endif
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#ifdef RAMP_CHECK
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unsigned prev=0;
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int started = 0;
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#endif
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unsigned command;
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unsigned underflow;
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#if (DSD_CHANS_DAC != 0)
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unsigned dsdMarker = DSD_MARKER_2; /* This alternates between DSD_MARKER_1 and DSD_MARKER_2 */
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int dsdCount = 0;
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int everyOther = 1;
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unsigned dsdSample_l = 0x96960000;
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unsigned dsdSample_r = 0x96960000;
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#endif
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unsigned underflowWord = 0;
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#if NUM_USB_CHAN_IN > 0
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for (int i=0;i<NUM_USB_CHAN_IN;i++)
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{
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samplesIn[i] = 0;
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samplesInPrev[i] = 0;
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}
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#endif
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#if(DSD_CHANS_DAC != 0)
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if(dsdMode == DSD_MODE_DOP)
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underflowWord = 0xFA969600;
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else if(dsdMode == DSD_MODE_NATIVE)
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{
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underflowWord = 0x96969696;
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}
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#endif
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outuint(c_out, 0);
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/* Check for sample freq change or new samples from mixer*/
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if(testct(c_out))
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{
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unsigned command = inct(c_out);
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#ifndef CODEC_MASTER
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// Set clocks low
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p_lrclk <: 0;
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p_bclk <: 0;
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#if(DSD_CHANS_DAC != 0)
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/* DSD Clock might not be shared with lrclk or bclk... */
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p_dsd_clk <: 0;
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#endif
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#endif
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#if (DSD_CHANS_DAC > 0)
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if(dsdMode == DSD_MODE_DOP)
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dsdMode = DSD_MODE_OFF;
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#endif
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return command;
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}
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else
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{
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underflow = inuint(c_out);
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#ifndef MIXER // Interfaces straight to decouple()
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#if NUM_USB_CHAN_IN > 0
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#pragma loop unroll
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for(int i = 0; i < NUM_USB_CHAN_IN; i++)
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{
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outuint(c_out, samplesIn[i]);
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}
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#endif
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#if NUM_USB_CHAN_OUT > 0
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if(underflow)
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{
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#pragma xta endpoint "received_underflow"
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#pragma loop unroll
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for(int i = 0; i < NUM_USB_CHAN_OUT; i++)
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{
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samplesOut[i] = underflowWord;
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}
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}
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else
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{
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#pragma loop unroll
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for(int i = 0; i < NUM_USB_CHAN_OUT; i++)
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{
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samplesOut[i] = inuint(c_out);
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}
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}
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#endif
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#else /* ifndef MIXER */
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#if NUM_USB_CHAN_OUT > 0
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if(underflow)
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{
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#pragma loop unroll
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for(int i = 0; i < NUM_USB_CHAN_OUT; i++)
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{
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samplesOut[i] = underflowWord;
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}
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}
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else
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{
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#pragma loop unroll
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for(int i = 0; i < NUM_USB_CHAN_OUT; i++)
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{
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int tmp = inuint(c_out);
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samplesOut[i] = tmp;
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}
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}
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#endif
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#if NUM_USB_CHAN_IN > 0
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#pragma loop unroll
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for(int i = 0; i < NUM_USB_CHAN_IN; i++)
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{
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outuint(c_out, samplesIn[i]);
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}
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#endif
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#endif
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}
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#ifndef CODEC_MASTER
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#if (DSD_CHANS_DAC > 0)
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if(dsdMode == DSD_MODE_OFF)
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{
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#endif
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/* b_clk must start high */
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p_bclk <: 0x80000000;
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sync(p_bclk);
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/* Clear I2S port buffers */
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clearbuf(p_lrclk);
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#if (I2S_CHANS_DAC != 0)
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for(int i = 0; i < I2S_WIRES_DAC; i++)
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{
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clearbuf(p_i2s_dac[i]);
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}
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#endif
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#if (I2S_CHANS_ADC != 0)
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for(int i = 0; i < I2S_WIRES_ADC; i++)
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{
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clearbuf(p_i2s_adc[i]);
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}
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#endif
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if(divide == 1)
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{
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#pragma xta endpoint "divide_1"
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p_lrclk <: 0 @ tmp;
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tmp += 100;
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/* Since BCLK is free-running, setup outputs/inputs at a known point in the future */
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#if (I2S_CHANS_DAC != 0)
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#pragma loop unroll
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for(int i = 0; i < I2S_WIRES_DAC; i++)
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{
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p_i2s_dac[i] @ tmp <: 0;
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}
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#endif
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p_lrclk @ tmp <: 0x7FFFFFFF;
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#if (I2S_CHANS_ADC != 0)
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for(int i = 0; i < I2S_WIRES_ADC; i++)
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{
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asm("setpt res[%0], %1"::"r"(p_i2s_adc[i]),"r"(tmp-1));
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}
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#endif
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}
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else
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{
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clearbuf(p_bclk);
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// asm("setpt res[%0], %1"::"r"(p_i2s_adc[0]),"r"(64));
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#if 1
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#if (I2S_CHANS_DAC != 0)
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/* Prefill the ports so data is input in advance */
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for(int i = 0; i < I2S_WIRES_DAC; i++)
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{
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p_i2s_dac[i] <: 0;
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}
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#endif
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p_lrclk <: 0xFFFFFFFF;
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doI2SClocks(divide);
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for(int i = 0; i < I2S_WIRES_DAC; i++)
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{
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p_i2s_dac[i] <: 0;
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}
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p_lrclk <: 0x7FFFFFFF;
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doI2SClocks(divide);
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#else
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for (int i = 0; i < I2S_WIRES_DAC; i++)
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{
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p_i2s_dac[i] @ 64 <: 0;
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}
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for (int i = 0; i < I2S_WIRES_ADC; i++)
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{
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asm("setpt res[%0], %1" :: "r"(p_i2s_adc[i]), "r"(63));
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}
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p_lrclk @ 31 <: 0;
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// clocks for previous outputs / inputs
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doI2SClocks(divide);
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p_lrclk <: 0;
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doI2SClocks(divide);
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p_lrclk <: 0;
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doI2SClocks(divide);
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#endif
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}
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#if (DSD_CHANS_DAC > 0)
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} /* if (!dsdMode) */
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else
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{
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/* p_dsd_clk must start high */
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p_dsd_clk <: 0x80000000;
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}
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#endif
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#else /* ifndef CODEC_MASTER */
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/* Wait for LRCLK edge */
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p_lrclk when pinseq(0) :> void;
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p_lrclk when pinseq(1) :> void;
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p_lrclk when pinseq(0) :> void;
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p_lrclk when pinseq(1) :> void;
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p_lrclk when pinseq(0) :> void @ tmp;
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tmp+=97;
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#if (I2S_CHANS_DAC != 0)
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#pragma loop unroll
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for(int i = 0; i < I2S_WIRES_DAC; i++)
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{
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p_i2s_dac[i] @ tmp <: 0;
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}
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#endif
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#if (I2S_CHANS_ADC != 0)
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#pragma loop unroll
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for(int i = 0; i < I2S_WIRES_ADC; i++)
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{
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asm("setpt res[%0], %1"::"r"(p_i2s_adc[i]),"r"(tmp+31));
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}
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#endif
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/* TODO In master mode, the i/o loop assumes L/RCLK = 32bit clocks. We should check this every interation
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* and resync if we got a bclk glitch */
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#endif
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/* Main Audio I/O loop */
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while (1)
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{
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outuint(c_out, 0);
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outuint(c_out, 0);
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/* Check for sample freq change (or other command) or new samples from mixer*/
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if(testct(c_out))
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@@ -509,9 +238,189 @@ chanend ?c_adc)
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#endif
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}
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return 0;
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}
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tmp = 0;
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/* I2S delivery thread */
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#pragma unsafe arrays
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unsigned static deliver(chanend c_out, chanend ?c_spd_out, unsigned divide, unsigned curSamFreq,
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#if(defined(SPDIF_RX) || defined(ADAT_RX))
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chanend c_dig_rx,
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#endif
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chanend ?c_adc)
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{
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#if (I2S_CHANS_ADC != 0) || defined(SPDIF)
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unsigned sample;
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#endif
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unsigned underflow = 0;
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#if NUM_USB_CHAN_OUT > 0
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unsigned samplesOut[NUM_USB_CHAN_OUT];
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#endif
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#if NUM_USB_CHAN_IN > 0
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unsigned samplesIn[NUM_USB_CHAN_IN];
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unsigned samplesInPrev[NUM_USB_CHAN_IN];
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#endif
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unsigned tmp;
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#if (I2S_CHANS_ADC != 0)
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unsigned index;
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#endif
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#ifdef RAMP_CHECK
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unsigned prev=0;
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int started = 0;
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#endif
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#if (DSD_CHANS_DAC != 0)
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unsigned dsdMarker = DSD_MARKER_2; /* This alternates between DSD_MARKER_1 and DSD_MARKER_2 */
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int dsdCount = 0;
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int everyOther = 1;
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unsigned dsdSample_l = 0x96960000;
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unsigned dsdSample_r = 0x96960000;
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#endif
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unsigned underflowWord = 0;
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#if NUM_USB_CHAN_IN > 0
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for (int i=0;i<NUM_USB_CHAN_IN;i++)
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{
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samplesIn[i] = 0;
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samplesInPrev[i] = 0;
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}
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#endif
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#if(DSD_CHANS_DAC != 0)
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if(dsdMode == DSD_MODE_DOP)
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underflowWord = 0xFA969600;
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else if(dsdMode == DSD_MODE_NATIVE)
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{
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underflowWord = 0x96969696;
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}
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#endif
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unsigned command = DoSampleTransfer(c_out, samplesOut, samplesIn, underflowWord);
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if(command)
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{
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return command;
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}
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#ifndef CODEC_MASTER
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#if (DSD_CHANS_DAC > 0)
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if(dsdMode == DSD_MODE_OFF)
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{
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#endif
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/* b_clk must start high */
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p_bclk <: 0x80000000;
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sync(p_bclk);
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/* Clear I2S port buffers */
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clearbuf(p_lrclk);
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#if (I2S_CHANS_DAC != 0)
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for(int i = 0; i < I2S_WIRES_DAC; i++)
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{
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clearbuf(p_i2s_dac[i]);
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}
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#endif
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#if (I2S_CHANS_ADC != 0)
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for(int i = 0; i < I2S_WIRES_ADC; i++)
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{
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clearbuf(p_i2s_adc[i]);
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}
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#endif
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if(divide == 1)
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{
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#pragma xta endpoint "divide_1"
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p_lrclk <: 0 @ tmp;
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tmp += 100;
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/* Since BCLK is free-running, setup outputs/inputs at a known point in the future */
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#if (I2S_CHANS_DAC != 0)
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#pragma loop unroll
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for(int i = 0; i < I2S_WIRES_DAC; i++)
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{
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p_i2s_dac[i] @ tmp <: 0;
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}
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#endif
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p_lrclk @ tmp <: 0x7FFFFFFF;
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#if (I2S_CHANS_ADC != 0)
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for(int i = 0; i < I2S_WIRES_ADC; i++)
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{
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asm("setpt res[%0], %1"::"r"(p_i2s_adc[i]),"r"(tmp-1));
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}
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#endif
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}
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else
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{
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/* Initialisation to get DAC buffered i2s ports inline with ADC ports */
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#if (I2S_CHANS_DAC != 0)
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for(int i = 0; i < I2S_WIRES_DAC; i++)
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{
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p_i2s_dac[i] <: 0;
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}
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#endif
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p_lrclk <: 0xFFFFFFFF;
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doI2SClocks(divide);
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#if (I2S_CHANS_DAC != 0)
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for(int i = 0; i < I2S_WIRES_DAC; i++)
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{
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p_i2s_dac[i] <: 0;
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}
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#endif
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p_lrclk <: 0x7FFFFFFF;
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doI2SClocks(divide);
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}
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#if (DSD_CHANS_DAC > 0)
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} /* if (!dsdMode) */
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else
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{
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/* p_dsd_clk must start high */
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p_dsd_clk <: 0x80000000;
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}
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#endif
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#else /* ifndef CODEC_MASTER */
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/* Wait for LRCLK edge */
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p_lrclk when pinseq(0) :> void;
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p_lrclk when pinseq(1) :> void;
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p_lrclk when pinseq(0) :> void;
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p_lrclk when pinseq(1) :> void;
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p_lrclk when pinseq(0) :> void @ tmp;
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tmp+=97;
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#if (I2S_CHANS_DAC != 0)
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#pragma loop unroll
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for(int i = 0; i < I2S_WIRES_DAC; i++)
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{
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p_i2s_dac[i] @ tmp <: 0;
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}
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#endif
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#if (I2S_CHANS_ADC != 0)
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#pragma loop unroll
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for(int i = 0; i < I2S_WIRES_ADC; i++)
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{
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asm("setpt res[%0], %1"::"r"(p_i2s_adc[i]),"r"(tmp+31));
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}
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#endif
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/* TODO In master mode, the i/o loop assumes L/RCLK = 32bit clocks. We should check this every interation
|
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* and resync if we got a bclk glitch */
|
||||
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#endif
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/* Main Audio I/O loop */
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while (1)
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{
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unsigned command = DoSampleTransfer(c_out, samplesOut, samplesIn, underflowWord);
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if(command)
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return command;
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#if (DSD_CHANS_DAC != 0) && (NUM_USB_CHAN_OUT > 0)
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if(dsdMode == DSD_MODE_NATIVE)
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{
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@@ -621,7 +530,7 @@ chanend ?c_adc)
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{
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#if (I2S_CHANS_ADC != 0)
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/* Input prevous R sample into R in buffer */
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/* Input previous L sample into L in buffer */
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index = 0;
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#pragma loop unroll
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for(int i = 0; i < I2S_CHANS_ADC; i += 2)
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@@ -631,9 +540,6 @@ chanend ?c_adc)
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asm("in %0, res[%1]" : "=r"(sample) : "r"(p_i2s_adc[index++]));
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#if NUM_USB_CHAN_IN > 0
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samplesIn[i] = bitrev(sample);
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/* Store the previous left in left */
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//samplesIn[i-1] = samplesInPrev[i];
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#endif
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}
|
||||
#endif
|
||||
@@ -643,24 +549,22 @@ chanend ?c_adc)
|
||||
* after the falling edge on which LRCLK was toggled. (see I2S spec) */
|
||||
/* Generate clocks LR Clock low - LEFT */
|
||||
p_lrclk <: 0x80000000;
|
||||
// p_lrclk <: 0x7FFFFFFF;
|
||||
|
||||
#endif
|
||||
|
||||
#pragma xta endpoint "i2s_output_l"
|
||||
|
||||
#if (I2S_CHANS_DAC != 0) && (NUM_USB_CHAN_OUT != 0)
|
||||
tmp = 0;
|
||||
index = 0;
|
||||
#pragma loop unroll
|
||||
for(int i = 0; i < I2S_CHANS_DAC; i+=2)
|
||||
{
|
||||
p_i2s_dac[tmp++] <: bitrev(samplesOut[i]); /* Output RIGHT sample to DAC */
|
||||
p_i2s_dac[index++] <: bitrev(samplesOut[i]); /* Output Left sample to DAC */
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Clock out the LR Clock, the DAC data and Clock in the next sample into ADC */
|
||||
doI2SClocks(divide);
|
||||
|
||||
|
||||
|
||||
#if defined(SPDIF_RX) || defined(ADAT_RX)
|
||||
/* Sync with clockgen */
|
||||
inuint(c_dig_rx);
|
||||
@@ -692,7 +596,7 @@ chanend ?c_adc)
|
||||
#endif
|
||||
|
||||
#if (I2S_CHANS_ADC != 0)
|
||||
/* Input previous L ADC sample */
|
||||
/* Input previous right ADC sample */
|
||||
index = 0;
|
||||
#pragma loop unroll
|
||||
for(int i = 1; i < I2S_CHANS_ADC; i += 2)
|
||||
@@ -702,9 +606,7 @@ chanend ?c_adc)
|
||||
asm("in %0, res[%1]" : "=r"(sample) : "r"(p_i2s_adc[index++]));
|
||||
|
||||
#if NUM_USB_CHAN_IN > 0
|
||||
//samplesInPrev[i] = bitrev(sample);
|
||||
samplesIn[i] = bitrev(sample);
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
@@ -720,19 +622,16 @@ chanend ?c_adc)
|
||||
#endif
|
||||
|
||||
#ifndef CODEC_MASTER
|
||||
/* Clock out data (and LR clock) */
|
||||
p_lrclk <: 0x7FFFFFFF;
|
||||
//p_lrclk <: 0x80000000;
|
||||
#endif
|
||||
|
||||
|
||||
tmp = 0;
|
||||
index = 0;
|
||||
#pragma xta endpoint "i2s_output_r"
|
||||
#if (I2S_CHANS_DAC != 0) && (NUM_USB_CHAN_OUT != 0)
|
||||
#pragma loop unroll
|
||||
for(int i = 1; i < I2S_CHANS_DAC; i+=2)
|
||||
{
|
||||
p_i2s_dac[tmp++] <: bitrev(samplesOut[i]); /* Output LEFT sample to DAC */
|
||||
p_i2s_dac[index++] <: bitrev(samplesOut[i]); /* Output Right sample to DAC */
|
||||
}
|
||||
#endif
|
||||
doI2SClocks(divide);
|
||||
|
||||
Reference in New Issue
Block a user