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Fix for exception when entering DSD mode (also some tidies)

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This commit is contained in:
Ross Owen
2023-05-12 17:22:47 +01:00
parent 05dcb8f3ab
commit 981ea78be7
4 changed files with 22 additions and 27 deletions
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14
lib_xua/src/core/audiohub/xua_audiohub.xc
View File

@@ -701,17 +701,16 @@ void XUA_AudioHub(chanend ?c_aud, clock ?clk_audio_mclk, clock ?clk_audio_bclk,
numBits = 32;
}
#endif
divide = mClk / ( curSamFreq * numBits);
divide = mClk / (curSamFreq * numBits);
/* TODO; we should catch and handle the case when divide is 0. Currently design will lock up */
}
#if (DSD_CHANS_DAC > 0)
if(dsdMode)
{
/* Configure audio ports */
ConfigAudioPortsWrapper(
/* Configure audio ports */
ConfigAudioPortsWrapper(
#if (I2S_CHANS_DAC != 0) || (DSD_CHANS_DAC != 0)
p_dsd_dac,
DSD_CHANS_DAC,
@@ -724,7 +723,7 @@ void XUA_AudioHub(chanend ?c_aud, clock ?clk_audio_mclk, clock ?clk_audio_bclk,
null,
p_dsd_clk,
#endif
p_mclk_in, clk_audio_bclk, divide, curSamFreq, dsdMode);
p_mclk_in, clk_audio_bclk, divide, curSamFreq);
}
else
#endif
@@ -747,9 +746,8 @@ void XUA_AudioHub(chanend ?c_aud, clock ?clk_audio_mclk, clock ?clk_audio_bclk,
p_bclk,
#endif
#endif
p_mclk_in, clk_audio_bclk, divide, curSamFreq, dsdMode);
}
p_mclk_in, clk_audio_bclk, divide, curSamFreq);
}
{
unsigned curFreq = curSamFreq;

12
lib_xua/src/core/ports/audioports.c
View File

@@ -1,4 +1,4 @@
// Copyright 2013-2022 XMOS LIMITED.
// Copyright 2013-2023 XMOS LIMITED.
// This Software is subject to the terms of the XMOS Public Licence: Version 1.
#include <xs1.h>
@@ -9,17 +9,17 @@
#include "xua.h"
/* Note since DSD ports could be reused for I2S ports we do all the setup manually in C */
#if DSD_CHANS_DAC > 0
#if (DSD_CHANS_DAC > 0)
port p_dsd_dac[DSD_CHANS_DAC] = {
PORT_DSD_DAC0,
#endif
#if DSD_CHANS_DAC > 1
#if (DSD_CHANS_DAC > 1)
PORT_DSD_DAC1,
#endif
#if DSD_CHANS_DAC > 2
#if (DSD_CHANS_DAC > 2)
#error > 2 DSD chans currently not supported
#endif
#if DSD_CHANS_DAC > 0
#if (DSD_CHANS_DAC > 0)
};
port p_dsd_clk = PORT_DSD_CLK;
#endif
@@ -45,7 +45,7 @@ void ConfigAudioPortsWrapper(
port p_lrclk,
port p_bclk,
#endif
port p_mclk_in, clock clk_audio_bclk, unsigned int divide, unsigned curSamFreq, unsigned int dsdMode)
port p_mclk_in, clock clk_audio_bclk, unsigned int divide, unsigned curSamFreq)
{
ConfigAudioPorts(
#if (I2S_CHANS_DAC != 0) || (DSD_CHANS_DAC != 0)

6
lib_xua/src/core/ports/audioports.h
View File

@@ -1,4 +1,4 @@
// Copyright 2011-2022 XMOS LIMITED.
// Copyright 2011-2023 XMOS LIMITED.
// This Software is subject to the terms of the XMOS Public Licence: Version 1.
#ifndef _AUDIOPORTS_H_
#define _AUDIOPORTS_H_
@@ -79,7 +79,7 @@ void ConfigAudioPortsWrapper(
buffered in port:32 p_bclk,
#endif
#endif
in port p_mclk_in, clock clk_audio_bclk, unsigned int divide, unsigned curSamFreq, unsigned int dsdMode);
in port p_mclk_in, clock clk_audio_bclk, unsigned int divide, unsigned curSamFreq);
#else
void ConfigAudioPortsWrapper(
@@ -95,7 +95,7 @@ void ConfigAudioPortsWrapper(
port p_lrclk,
port p_bclk,
#endif
port p_mclk_in, clock clk_audio_bclk, unsigned int divide, unsigned curSamFreq, unsigned int dsdMode);
port p_mclk_in, clock clk_audio_bclk, unsigned int divide, unsigned curSamFreq);
#endif /* __XC__*/

17
lib_xua/src/core/ports/audioports.xc
View File

@@ -1,4 +1,4 @@
// Copyright 2011-2022 XMOS LIMITED.
// Copyright 2011-2023 XMOS LIMITED.
// This Software is subject to the terms of the XMOS Public Licence: Version 1.
#include <xs1.h>
#include <platform.h>
@@ -6,9 +6,7 @@
#include "xua.h"
#include "audioports.h"
//extern in port p_mclk_in;
extern clock clk_audio_mclk;
//extern clock clk_audio_bclk;
void ConfigAudioPorts(
#if (I2S_CHANS_DAC != 0) || (DSD_CHANS_DAC != 0)
@@ -58,7 +56,7 @@ void ConfigAudioPorts(
}
#endif
#if (I2S_CHANS_DAC != 0)
#if (I2S_CHANS_DAC != 0)|| (DSD_CHANS_DAC != 0)
for(int i = 0; i < numPortsDac; i++)
{
clearbuf(p_i2s_dac[i]);
@@ -82,7 +80,7 @@ void ConfigAudioPorts(
/* Some adustments for timing. Sample ADC lines on negative edge and add some delay */
if(XUA_PCM_FORMAT == XUA_PCM_FORMAT_TDM)
{
for(int i = 0; i < I2S_WIRES_ADC; i++)
for(int i = 0; i < numPortsAdc; i++)
{
set_port_sample_delay(p_i2s_adc[i]);
set_pad_delay(p_i2s_adc[i], 4);
@@ -91,7 +89,6 @@ void ConfigAudioPorts(
#endif
#elif (CODEC_MASTER)
/* Stop bit and master clock blocks */
stop_clock(clk_audio_bclk);
@@ -112,9 +109,9 @@ void ConfigAudioPorts(
set_clock_fall_delay(clk_audio_bclk, bClkDelay_fall);
#endif
#if (I2S_CHANS_DAC != 0)
/* Clock I2S output data ports from b-clock clock block */
for(int i = 0; i < I2S_WIRES_DAC; i++)
#if (I2S_CHANS_DAC != 0) || (DSD_CHANS_DAC != 0)
/* Clock I2S/DSD output data ports from b-clock clock block */
for(int i = 0; i < numPortsDac; i++)
{
configure_out_port_no_ready(p_i2s_dac[i], clk_audio_bclk, 0);
}
@@ -122,7 +119,7 @@ void ConfigAudioPorts(
#if (I2S_CHANS_ADC != 0)
/* Clock I2S input data ports from clock block */
for(int i = 0; i < I2S_WIRES_ADC; i++)
for(int i = 0; i < numPortsAdc; i++)
{
configure_in_port_no_ready(p_i2s_adc[i], clk_audio_bclk);
}