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Another crack the the master mode LR swap issue.

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This commit is contained in:
Ross Owen
2014-01-23 17:59:26 +00:00
parent 4c4cf16204
commit b2660cf04e
1 changed files with 12 additions and 13 deletions
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25
module_usb_audio/audio.xc
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@@ -351,23 +351,13 @@ static inline void doI2SClocks(unsigned divide)
#else /* ifndef CODEC_MASTER */ #else /* ifndef CODEC_MASTER */
/* Wait for LRCLK edge */ /* Wait for LRCLK edge */
p_lrclk when pinseq(1) :> void;
p_lrclk when pinseq(0) :> void; p_lrclk when pinseq(0) :> void;
p_lrclk when pinseq(1) :> void; p_lrclk when pinseq(1) :> void;
p_lrclk when pinseq(0) :> void; p_lrclk when pinseq(0) :> void;
p_lrclk when pinseq(1) :> void @ tmp; p_lrclk when pinseq(1) :> void;
tmp += 96; p_lrclk when pinseq(0) :> void @ tmp;
tmp+=95;
#if (I2S_CHANS_ADC != 0)
#pragma loop unroll
for(int i = 0; i < I2S_WIRES_ADC; i++)
{
asm("setpt res[%0], %1"::"r"(p_i2s_adc[i]),"r"(tmp));
}
#endif
#if (I2S_CHANS_DAC != 0) #if (I2S_CHANS_DAC != 0)
tmp+=33;
#pragma loop unroll #pragma loop unroll
for(int i = 0; i < I2S_WIRES_DAC; i++) for(int i = 0; i < I2S_WIRES_DAC; i++)
{ {
@@ -375,6 +365,15 @@ static inline void doI2SClocks(unsigned divide)
} }
#endif #endif
#if (I2S_CHANS_ADC != 0)
tmp += 33;
#pragma loop unroll
for(int i = 0; i < I2S_WIRES_ADC; i++)
{
asm("setpt res[%0], %1"::"r"(p_i2s_adc[i]),"r"(tmp));
}
#endif
/* TODO In master mode, the i/o loop assumes L/RCLK = 32bit clocks. We should check this every interation /* TODO In master mode, the i/o loop assumes L/RCLK = 32bit clocks. We should check this every interation
* and resync if we got a bclk glitch */ * and resync if we got a bclk glitch */