forked from PAWPAW-Mirror/lib_xua
Added new iic files
This commit is contained in:
Ross Owen
36
module_usb_aud_shared/iic/iic.h
Executable file
36
module_usb_aud_shared/iic/iic.h
Executable file
@@ -0,0 +1,36 @@
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#ifndef IIC_H_
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#define IIC_H_
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#include <xccompat.h>
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int iic_initialise(timer t, port p_scl, port p_sda);
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// Write to IIC device
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#if defined __XC__
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int iic_writeC(unsigned int address, unsigned int reg, unsigned char data[], unsigned int numBytes, chanend ?c,
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port ?p_scl, port ?p_sda);
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#elif defined __STDC__
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int iic_writeC(unsigned int address, unsigned int reg, unsigned char data[], unsigned int numBytes, chanend c,
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port p_scl, port p_sda);
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#endif
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int iic_write(unsigned int address, unsigned int reg, unsigned char data[], unsigned int numBytes, timer t,
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port p_scl, port p_sda);
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// Read from IIC device
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// It receives numBytes, acking each one and does not ack the final byte
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#if defined __XC__
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int iic_readC(unsigned int address, unsigned int reg, unsigned char data[], unsigned int numBytes, chanend ?c,
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port ?p_scl, port ?p_sda);
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#elif defined __STDC__
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int iic_readC(unsigned int address, unsigned int reg, unsigned char data[], unsigned int numBytes, chanend c,
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port p_scl, port p_sda);
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#endif
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int iic_read(unsigned int address, unsigned int reg, unsigned char data[], unsigned int numBytes, timer t, port p_scl, port p_sda);
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// iic_phy_wait
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// Wait a certain number of cycles
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void iic_phy_wait(unsigned delay, timer t);
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#endif /*IIC_H_*/
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454
module_usb_aud_shared/iic/iic.xc
Executable file
454
module_usb_aud_shared/iic/iic.xc
Executable file
@@ -0,0 +1,454 @@
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/*
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* @ModuleName iic
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* @Author Ali Dixon, Corin Rathbone & Ross Owen
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* @Date 30/07/2008
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* @Version 1.2
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* @Description IIC bus interface
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*
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* The copyrights, all other intellectual and industrial
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* property rights are retained by XMOS and/or its licensors.
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* Terms and conditions covering the use of this code can
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* be found in the Xmos End User License Agreement.
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*
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* Copyright XMOS Ltd 2008
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*/
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#include <xs1.h>
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#include <stdio.h>
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#include "print.h"
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#include "iic.h"
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#include "freqConst.h"
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#define EXPECT_ACK 0
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#define IIC_WE 0
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#define IIC_RE 1
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#define iic_bittime (2000) // ref clock cycles per iic bit
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// times are in units of 10ns
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#define iic_scl_high_time (iic_bittime >> 1)
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#define iic_scl_low_time (iic_bittime >> 1)
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#define iic_bus_free_time iic_bittime
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#define iic_start_cond_setup_time iic_bittime
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#define iic_start_cond_hold_time iic_bittime
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#define iic_write_cycle_time (5000 * XS1_TIMER_MHZ) // 5ms
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#define iic_write_ack_poll_time ( 50 * XS1_TIMER_MHZ) // 50us
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//extern port p_i2c_scl;
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#define PORT_IIC_SCL p_scl
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//extern port p_i2c_sda;
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#define PORT_IIC_SDA p_sda
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extern timer i2ctimer;
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#define SCLHIGH() \
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{ \
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int onedetect = 0; \
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while (1) { \
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int val; \
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PORT_IIC_SCL :> val; \
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if (val == 1) { \
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onedetect++; \
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if (onedetect > 20) \
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break; \
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} else { \
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onedetect = 0; \
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} \
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} \
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}
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// Wait for the specified amount of time
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void iic_phy_wait(unsigned delay, timer t)
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{
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unsigned int time;
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t :> time;
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t when timerafter (time + delay) :> unsigned int tmp;
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}
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// Release the bus
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int iic_initialise(timer t, port p_scl, port p_sda)
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{
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int returnCode = 0;
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unsigned int scl_value;
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unsigned int sda_value;
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scl_value = 0;
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sda_value = 0;
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while ((scl_value != 1) || (sda_value != 1))
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{
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PORT_IIC_SCL :> scl_value;
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PORT_IIC_SDA :> sda_value;
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}
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iic_phy_wait(10 * iic_bittime, t);
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scl_value = 0;
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sda_value = 0;
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while ((scl_value != 1) || (sda_value != 1))
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{
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PORT_IIC_SCL :> scl_value;
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PORT_IIC_SDA :> sda_value;
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}
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return returnCode;
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}
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// Generate start condition
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void iic_phy_master_start(timer t, port p_scl, port p_sda)
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{
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SCLHIGH();
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PORT_IIC_SDA <: 1;
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iic_phy_wait(iic_start_cond_setup_time, t);
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PORT_IIC_SDA <: 0;
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iic_phy_wait(iic_start_cond_hold_time, t);
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PORT_IIC_SCL <: 0;
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}
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// Generate stop condition
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void iic_phy_master_stop(timer t, port p_scl, port p_sda)
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{
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PORT_IIC_SDA <: 0;
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iic_phy_wait(iic_scl_low_time, t);
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SCLHIGH();
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iic_phy_wait(iic_scl_high_time, t);
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PORT_IIC_SDA <: 1;
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iic_phy_wait(iic_bus_free_time, t);
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}
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// Send a bit
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unsigned int iic_phy_sendBit(unsigned int bit, timer t, port p_scl, port p_sda)
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{
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unsigned int time;
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t :> time;
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PORT_IIC_SDA <: bit;
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time += iic_scl_low_time;
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t when timerafter(time) :> time;
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SCLHIGH();
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t :> time;
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time += iic_scl_high_time;
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t when timerafter(time) :> time;
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PORT_IIC_SCL <: 0; // set clock low
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return 0;
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}
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// Receive a bit
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unsigned int iic_phy_receiveBit(timer t, port p_scl, port p_sda)
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{
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unsigned int bit;
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unsigned int time;
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t :> time;
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PORT_IIC_SDA :> int tmp;
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time += iic_scl_low_time;
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t when timerafter(time) :> time;
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SCLHIGH();
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t :> time;
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PORT_IIC_SDA :> bit;
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time += iic_scl_high_time;
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t when timerafter(time) :> time;
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PORT_IIC_SCL <: 0; // set clock low
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time += iic_scl_low_time;
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t when timerafter(time) :> time;
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return bit;
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}
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// Send a byte
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int iic_phy_sendByte(unsigned int inByte, unsigned int expectAck, timer t, port p_scl, port p_sda)
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{
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unsigned int bitCount;
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unsigned int bit;
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unsigned int byte;
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unsigned int ack;
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unsigned int time;
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byte = inByte;
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bitCount = 0;
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t :> time;
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while (bitCount < 8)
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{
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bit = (byte & 0x80) >> 7;
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time += (iic_scl_low_time>>1);
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t when timerafter(time) :> time;
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PORT_IIC_SDA <: bit;
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time += (iic_scl_low_time>>1);
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t when timerafter(time) :> time;
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SCLHIGH();
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t :> time;
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byte = byte << 1;
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bitCount = bitCount + 1;
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time += iic_scl_high_time;
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t when timerafter(time) :> time;
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PORT_IIC_SCL <: 0; // set clock low
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}
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PORT_IIC_SDA :> int tmp;
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ack = iic_phy_receiveBit(t, p_scl, p_sda);
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if (ack != expectAck)
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{
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return 1;
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}
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else
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{
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return 0;
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}
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}
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// Receive a byte
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unsigned int iic_phy_receiveByte(unsigned int ack, timer t, port p_scl, port p_sda)
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{
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unsigned int bitCount;
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unsigned int bit;
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unsigned int time;
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unsigned int byte;
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byte = 0;
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bitCount = 0;
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t :> time;
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// set to input
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PORT_IIC_SDA :> int tmp;
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while (bitCount < 8)
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{
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time += iic_scl_low_time;
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t when timerafter(time) :> time;
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SCLHIGH();
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t :> time;
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PORT_IIC_SDA :> bit;
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byte = (byte << 1) | bit;
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bitCount = bitCount + 1;
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time += iic_scl_high_time;
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t when timerafter(time) :> time;
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PORT_IIC_SCL <: 0; // set clock low
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}
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PORT_IIC_SDA :> int tmp;
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iic_phy_sendBit(ack, t, p_scl, p_sda);
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return byte;
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}
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// Poll to determine when write completes
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unsigned int iic_checkWriteComplete(unsigned int address, timer t, port p_scl, port p_sda)
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{
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unsigned int time;
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t :> time;
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iic_phy_master_start(t, p_scl, p_sda);
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do
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{
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iic_phy_master_stop(t, p_scl, p_sda);
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t when timerafter(time + iic_write_ack_poll_time) :> time;
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iic_phy_master_start(t, p_scl, p_sda);
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} while (iic_phy_sendByte((address << 1) | IIC_WE, EXPECT_ACK, t, p_scl, p_sda));
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if (iic_phy_sendByte(0, EXPECT_ACK, t, p_scl, p_sda))
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{
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}
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if (iic_phy_sendByte(0, EXPECT_ACK, t, p_scl, p_sda))
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{
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}
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iic_phy_master_stop(t, p_scl, p_sda);
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iic_phy_master_start(t, p_scl, p_sda);
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iic_phy_sendByte((address << 1) | IIC_WE, EXPECT_ACK, t, p_scl, p_sda);
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return 0;
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}
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// Write to IIC device
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int iic_writeC(unsigned int address, unsigned int reg, char data[], unsigned int numBytes, chanend ?c,
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port ?p_scl, port ?p_sda)
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{
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/* If null channel end arg passed in use i2c ports */
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if(isnull(c))
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{
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return iic_write(address, reg, data, numBytes, i2ctimer, p_scl, p_sda);
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}
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else
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{
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int read;
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int retVal;
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c <: 1; // isWrite
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c <: (address << 1);
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c <: reg;
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c <: numBytes;
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for(int i = 0; i!= numBytes; i++)
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{
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read = data[i];
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c <: read;
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}
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c :> retVal;
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return retVal;
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}
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}
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void iic_wait(timer t, unsigned us)
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{
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unsigned time;
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t :> time;
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time += us * 100;
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t when timerafter(time) :> void;
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}
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#define COPROCESSOR_LOOPS 10
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int iic_write(unsigned int address, unsigned int reg, char data[], unsigned int numBytes, timer t, port p_scl, port p_sda)
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{
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unsigned int i = 0;
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//printf("Start of iic_write(0x%04x, 0x%04x, 0x%02x, %d)\n", address, reg, data[0], numBytes);
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iic_phy_master_start(t, p_scl, p_sda);
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i = COPROCESSOR_LOOPS;
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while(i)
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{
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iic_phy_master_start(t, p_scl, p_sda);
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if(0 == iic_phy_sendByte((address << 1) | IIC_WE, EXPECT_ACK, t, p_scl, p_sda))
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break;
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iic_wait(t, 600);
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i--;
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}
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if(!i)
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{
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//printstrln("W1");
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return 1;
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}
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if (iic_phy_sendByte((reg), EXPECT_ACK, t, p_scl, p_sda))
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return 3;
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for ( i=0; i<numBytes; i++)
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{
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if (iic_phy_sendByte(data[i], EXPECT_ACK, t, p_scl, p_sda))
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break;
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}
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iic_phy_master_stop(t, p_scl, p_sda);
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iic_checkWriteComplete(address, t, p_scl, p_sda);
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return 0;
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}
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// Read from IIC device
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// It receives numBytes, acking each one and does not ack the final byte
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int iic_readC(unsigned int address, unsigned int reg, char data[], unsigned int numBytes, chanend ?c,
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port ?p_scl, port ?p_sda)
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{
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/* If null channend argument passed in use i2c ports */
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if(isnull(c))
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{
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return iic_read(address, reg, data, numBytes, i2ctimer, p_scl, p_sda);
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}
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else
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{
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int read;
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int retVal;
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c <: 0; // isWrite
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c <: (address << 1); // This is getting silly, this shifts it up to a full 8 bit address so i2c_thread can shift it down again so the real iic_read can shift it up again.
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c <: reg;
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c <: numBytes;
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for(int i = 0; i!= numBytes; i++)
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{
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c :> read;
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data[i] = read;
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}
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c :> retVal;
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return retVal;
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}
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}
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int iic_read(unsigned int address, unsigned int reg, char data[], unsigned int numBytes, timer t, port p_scl, port p_sda)
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{
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unsigned int i;
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iic_phy_master_start(t, p_scl, p_sda);
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i = COPROCESSOR_LOOPS;
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while(i)
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{
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iic_phy_master_start(t, p_scl, p_sda);
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if(0 == iic_phy_sendByte((address << 1) | IIC_WE, EXPECT_ACK, t, p_scl, p_sda))
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break;
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iic_wait(t, 600);
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i--;
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}
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if(!i)
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{
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//printstrln("S1");
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return 1;
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}
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if (iic_phy_sendByte((reg), EXPECT_ACK, t, p_scl, p_sda))
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{
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//printstrln("S2");
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return 1;
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}
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iic_phy_master_stop(t, p_scl, p_sda);
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i = COPROCESSOR_LOOPS;
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while(i)
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{
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iic_phy_master_start(t, p_scl, p_sda);
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if(0 == iic_phy_sendByte((address << 1) | IIC_RE, EXPECT_ACK, t, p_scl, p_sda))
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break;
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iic_wait(t, 600);
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i--;
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}
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if(!i)
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{
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//printstrln("S3");
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return 1;
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}
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for (i=0; i<numBytes-1; i++)
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{
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data[i] = iic_phy_receiveByte(0, t, p_scl, p_sda);
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}
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// printf("Start of iic_read(0x%04x, 0x%04x, 0x%02x, %d)\n", address, reg, data[0], numBytes);
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// receive final byte and dont ack to signal end of transfer
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data[i] = iic_phy_receiveByte(1, t, p_scl, p_sda);
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iic_phy_master_stop(t, p_scl, p_sda);
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return 0;
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}
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