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Audio port config functions now get passed SR. Simple clock delay (falling edge) added for xCORE-slave mode when bclk >= 20MHz

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This commit is contained in:
Ross Owen
2016-03-16 15:21:17 +00:00
parent 577d68a08b
commit 0ed22a0417
4 changed files with 21 additions and 9 deletions
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4
module_usb_audio/audio.xc
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@@ -1098,7 +1098,7 @@ chanend ?c_config, chanend ?c
null,
p_dsd_clk,
#endif
divide, dsdMode);
divide, curSamFreq, dsdMode);
}
else
#endif
@@ -1122,7 +1122,7 @@ chanend ?c_config, chanend ?c
p_bclk,
#endif
#endif
divide, dsdMode);
divide, curSamFreq, dsdMode);
}

4
module_usb_audio/ports/audioports.c
View File

@@ -43,7 +43,7 @@ void ConfigAudioPortsWrapper(
port p_lrclk,
port p_bclk,
#endif
unsigned int divide, unsigned int dsdMode)
unsigned int divide, unsigned curSamFreq, unsigned int dsdMode)
{
ConfigAudioPorts(
#if (I2S_CHANS_DAC != 0) || (DSD_CHANS_DAC != 0)
@@ -56,5 +56,5 @@ unsigned int divide, unsigned int dsdMode)
#endif
p_lrclk,
p_bclk,
divide);
divide, curSamFreq);
}

8
module_usb_audio/ports/audioports.h
View File

@@ -26,7 +26,7 @@ void ConfigAudioPorts(
in port p_bclk,
#endif
#endif
unsigned int divide);
unsigned int divide, unsigned int curSamFreq);
#else
void ConfigAudioPorts(
@@ -49,7 +49,7 @@ void ConfigAudioPorts(
port p_bclk,
#endif
#endif
unsigned int divide);
unsigned int divide, unsigned int curSamFreq);
#endif /* __XC__*/
@@ -74,7 +74,7 @@ void ConfigAudioPortsWrapper(
in port p_bclk,
#endif
#endif
unsigned int divide, unsigned int dsdMode);
unsigned int divide, unsigned curSamFreq, unsigned int dsdMode);
#else
void ConfigAudioPortsWrapper(
@@ -90,7 +90,7 @@ void ConfigAudioPortsWrapper(
port p_lrclk,
port p_bclk,
#endif
unsigned int divide, unsigned int dsdMode);
unsigned int divide, unsigned curSamFreq, unsigned int dsdMode);
#endif /* __XC__*/

14
module_usb_audio/ports/audioports.xc
View File

@@ -28,7 +28,7 @@ void ConfigAudioPorts(
in port p_bclk,
#endif
#endif
unsigned int divide)
unsigned int divide, unsigned curSamFreq)
{
#if !defined(CODEC_MASTER)
/* Note this call to stop_clock() will pause forever if the port clocking the clock-block is not low.
@@ -116,6 +116,18 @@ unsigned int divide)
/* Clock bclk clock-block from bclk pin */
configure_clock_src(clk_audio_bclk, p_bclk);
/* Do some clocking shifting to get data in the valid window */
/* E.g. Only shift when running at 88.2+ kHz TDM slave */
int bClkDelay_fall = 0;
if(curSamFreq * I2S_CHANS_PER_FRAME * 32 >= 20000000)
{
/* 18 * 2ns = 36ns. This results in a -4ns (36 - 40) shift at 96KHz and -8ns (36 - 44) at 88.4KHz */
bClkDelay_fall = 18;
}
set_clock_fall_delay(clk_audio_bclk, bClkDelay_fall);
#if (I2S_CHANS_DAC != 0)
/* Clock I2S output data ports from b-clock clock block */
for(int i = 0; i < I2S_WIRES_DAC; i++)